Thin film transistor array panel and manufacturing method thereof

A method of manufacturing a thin film transistor array panel, comprising:

• forming a polysilicon layer on a substrate;
• depositing a gate insulating layer on the substrate;
• depositing a doped silicon layer on the gate insulating layer;
• depositing a conductive film on the doped silicon layer;
• forming a photoresist relative to the conductive film;
• patterning the conductive film by isotropic etching using the photoresist as an etch mask to form a gate electrode;
• patterning the doped silicon layer by anisotropic etching using the photoresist as an etch mask to form an impurity layer;
• forming source and drain regions having a first impurity concentration by introducing impurities into the polysilicon layer using the impurity layer as a mask;
• forming lightly doped regions having a second impurity concentration lower than the first impurity concentration by introducing impurities into the polysilicon member using the gate electrode as a mask;
• forming an interlayer insulating layer covering the gate electrode having contact holes respectively exposing the source and the drain regions;
• and
• forming source and drain electrodes on the interlayer insulating layer, the source and drain electrodes respectively connected to the source and the drain regions via the contact holes.

A thin film transistor array panel comprising:

• an insulating layer;
• a gate conductor transmitting gate signals;
• and,
• an impurity layer doped with impurities and interposed between the insulating layer and the gate conductor.