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US 2006/0065893 A1Published application
Method of forming gate by using layer-growing process and gate structure manufactured thereby
AssigneeSamsung Electronics Co., Ltd.
InventorsYou-seung Jin, Shigenobu Maeda
Life of this patent
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Abstract
Provided are a method of forming a gate by using layer growth, and a gate structure formed thereby. A gate dielectric layer and a seed layer are sequentially formed on a substrate, and then a mask is used to selectively grow a gate layer on the seed layer. An exposed portion of the seed layer surrounding the gate layer, and the gate layer, are isotropically etched to form a gate.
Claims20
A method of forming a gate of a transistor, the method comprising:
- forming a gate dielectric layer on a substrate;
- forming a seed layer on the gate dielectric layer;
- forming a mask on the seed layer to selectively grow a gate layer;
- selectively growing the gate layer on a portion of the seed layer exposed by the mask;
- selectively removing the mask;
- and
- isotropically etching exposed portions of the seed layer and the gate layer to form a gate such that the gate has a smaller line width than the gate layer.
4 more elements
A method of forming a gate of a transistor, the method comprising:
- forming a gate dielectric layer on a substrate;
- forming a seed layer on the gate dielectric layer;
- forming on the seed layer a mask having an open region exposing a portion of the seed layer to selectively grow a gate layer on the exposed portion of the seed layer;
- forming spacers covering a portion of the exposed portion of the seed layer on sidewalls of the open region of the mask such that a line width of the exposed portion of the seed layer is less than an upper line width of the open region;
- selectively growing the gate layer on the portion of the seed layer exposed by the mask and the spacer;
- selectively removing the mask and the spacer;
- and
- isotropically etching exposed portions of the seed layer and the gate layer to form a gate such that a lower line width of the gate is less than a line width of the gate layer and an upper line width of the gate is greater than the lower line width of the gate.
5 more elements
A gate of a transistor, the gate comprising:
- a seed layer formed on a gate dielectric layer on a substrate;
- and
- a gate layer formed by selectively growing silicon germanium on the seed layer.
A gate of a transistor, the gate comprising:
- a seed layer formed on a gate dielectric layer on a substrate;
- and
- a gate layer formed by selectively growing silicon germanium on the seed layer, wherein a lower line width of the gate layer is less than an upper line width of the gate layer.
Dependencies are inferred from the claim text.