Clock tree synthesis for low power consumption and low clock skew

A clock tree synthesis for low power consumption and low clock skew, comprising the steps of:

• inputting clock tree synthesis netlist including the electric parameter data of each of paths, timing of buffers and the power database;
• inputting the timing standard maximum of clock skew;
• determining the buffers according to the design standard via a design standard validator that calculates the signal inputting to the root of clock tree to each buffers, the transfer time of flip-flop and the output load of each buffer;
• balancing the clock tree load, and solving the conditions of departing from the specific database design standard and the clock tree skew greater than that of the design standard;
• changing the type of the buffer for quickly searching a feasible solution for reducing the power consumption of the clock tree;
• and
• using heuristic of the specific database and the processes of optimum based on simulating annealing method for searching the interconnect of the buffer on the clock tree to gain a optimization solution of the power consumption of the clock tree in all areas.