Method and apparatus for estimating parasitic capacitance
AssigneeSynopsys, Inc.
InventorsShabbir Batterywala, Narendra Shenoy, Madhav Desai
Life of this patent
Estimating the term…
Abstract
One embodiment of the present invention provides a system for estimating parasitic capacitance for an integrated circuit. During operation, the system reads a technology file, which describes the composition of a vertical cross-section of the integrated circuit. Next, the system reads a design file, which specifies the layout of the integrated circuit. The system then identifies a set of dielectric configurations based on information contained in the technology file. It then computes Green's function for each of these configurations. Next, the system estimates a parasitic capacitance using information contained in the design file and using the set of Green's functions.
Claims42
A method for estimating parasitic capacitance for an integrated circuit, the method comprising:
- reading a technology file, which describes the composition of a vertical cross-section of the integrated circuit;
- reading a design file, which specifies the layout of the integrated circuit;
- computing a set of Green's functions based on information contained in the technology file;
- and
- estimating a parasitic capacitance using information contained in the design file and using the set of Green's functions.
A method for identifying a set of dielectric configurations for a fabrication technology, the method comprising:
- reading a technology file, which describes the composition of a vertical cross-section of an integrated circuit manufactured using a fabrication technology;
- and
- identifying a set of dielectric configurations using information contained in the technology file;
- wherein the identified set of dielectric configurations contains dielectric configurations that are encountered by a capacitance estimation process during the execution of random walks.
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for estimating parasitic capacitance for an integrated circuit, the method comprising:
- reading a technology file, which describes the composition of a vertical cross-section of the integrated circuit;
- reading a design file, which specifies the layout of the integrated circuit;
- computing a set of Green's functions based on information contained in the technology file;
- and
- estimating a parasitic capacitance using information contained in the design file and using the set of Green's functions.
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for identifying a set of dielectric configurations for a fabrication technology, the method comprising:
- reading a technology file, which describes the composition of a vertical cross-section of an integrated circuit manufactured using a fabrication technology;
- and
- identifying a set of dielectric configurations using information contained in the technology file;
- wherein the identified set of dielectric configurations contains dielectric configurations that are encountered by a capacitance estimation process during the execution of random walks.
An apparatus for estimating parasitic capacitance for an integrated circuit, the apparatus comprising:
- a technology-reading mechanism configured to read a technology file, which describes the composition of a vertical cross-section of the integrated circuit;
- a design-reading mechanism configured to read a design file, which specifies the layout of the integrated circuit;
- a computing mechanism configured to compute a set of Green's functions based on information contained in the technology file;
- and
- a estimating mechanism configured to estimate a parasitic capacitance using information contained in the design file and using the set of Green's functions.
An apparatus for identifying a set of dielectric configurations for a fabrication technology, the apparatus comprising:
- a technology-reading mechanism configured to read a technology file, which describes the composition of a vertical cross-section of an integrated circuit manufactured using the fabrication technology;
- and
- an identifying mechanism configured to identify a set of dielectric configurations using information contained in the technology file;
- wherein the identified set of dielectric configurations contains dielectric configurations that are encountered by a capacitance estimation process during the execution of random walks.
Dependencies are inferred from the claim text.