Test method for determining the wire configuration for circuit carriers with components arranged thereon

A method of determining a connection configuration for a circuit carrier including at least one component arranged on the circuit carrier, the at least one component including internal lines connected to component connections in a prescribed order, and the component connections connected to circuit carrier connections on the circuit carrier, the method comprising:

• (a) applying prescribed test signals to the internal lines of the component using a controllable test signal generator integrated in the component;
• (b) obtaining output signals from the circuit carrier connections;
• and
• (c) identifying the respective output signals with the corresponding test signals applied to the internal lines of the component using an external test apparatus for determining the connection configuration between the component connections and the circuit carrier connections.

A memory module test system including a memory module having at least one memory chip arranged on the memory module, the memory chip including internal lines connected to memory chip connections in a prescribed order, and the memory module including memory module connections connected to the memory chip connections, the memory module test system comprising:

• (a) means for applying prescribed test signals to the internal lines of the memory chip, said means for applying integrated in the memory chip;
• connections and the memory chip control connections being connected to memory module control connections;
• and
• c) an external memory test apparatus connected to the external memory module connections, the external memory test apparatus operable to apply control signals to the memory module control connections and operable to receive output signals from the memory module data connections;
• d) wherein in a first test phase the external memory test apparatus is operable to provide to the memory module control connections control signals operable to activate the test signal generator;
• e) wherein in a second test phase the internal test signal generator is operable to provide to the internal data lines of the memory chip prescribed test data signals in order to write test data to the memory chip, and wherein the external memory test apparatus is operable to provide to the memory module control connections control signals operable to deactivate the test signal generator;
• and
• f) wherein in a third test phase the external memory test apparatus is operable to read the written test data as output signals at the memory module data connections and compare the read test data with the written test data in order to ascertain the connection configuration between the memory chip data connections and the memory module data connections.
• (b) means for obtaining output signals from the memory module connections;
• and
• (c) means for determining the connection configuration between the memory chip connections and the memory module connections, said means for determining operable to identify the respective output signals from the memory module connections with the corresponding test signals applied to the internal lines of the memory chip.