Dynamic frequency scaling sequence for multi-gigahertz microprocessors
AssigneeInternational Business Machines Corporation
InventorsNathan Chelstrom, Mack Riley, Michael Wang, Stephen Weitzel
Life of this patent
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Abstract
The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.
Claims9
A method for reducing current spikes in a circuit when changing clocking frequencies, comprising:
- applying a first frequency to a clock distribution network;
- selecting a final frequency;
- applying the first frequency to a logic element over the clock distribution network;
- applying a hold signal to the logic element;
- changing the clock rate of the clock distribution network from the first frequency to the final frequency;
- and
- unapplying the hold signal to the logic element.
A system for reducing current spikes in a circuit when changing clocking frequencies, comprising:
- a frequency control logic;
- a phase locked loop coupled to the control logic;
- a clock distribution network coupled to the phase locked loop;
- a hold logic coupled to the frequency control logic;
- and
- a logic device coupled to clock distribution logic and the hold logic.
A computer program product for reducing current spikes in a circuit when changing clocking frequencies, the computer program product having a medium with a computer program embodied thereon, the computer program comprising:
- computer code for applying a first frequency to a clock distribution network;
- computer code for selecting a final frequency;
- computer code for applying the first frequency to a logic element over the clock distribution network;
- computer code for applying a hold signal to the logic element;
- computer code for changing the clock rate of the clock distribution network from the first frequency to the final frequency;
- and
- computer code for unapplying the hold signal to the logic element.
A processor for reducing current spikes in a circuit when changing clocking frequencies, the processor including a computer program comprising:
- computer code for applying a first frequency to a clock distribution network;
- computer code for selecting a final frequency;
- computer code for applying the first frequency to a logic element over the clock distribution network;
- computer code for applying a hold signal to the logic element;
- computer code for changing the clock rate of the clock distribution network from the first frequency to the final frequency;
- and
- computer code for unapplying the hold signal to the logic element.
Dependencies are inferred from the claim text.