Back to results
US 2006/0053326 A1Published application
Coordinating idle state transitions in multi-core processors
AssigneeIntel Corporation
InventorsAlon Naveh, Abraham Mendelson, Ittai Anati, Eliezer Weissmann
Life of this patent
Estimating the term…
Abstract
Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.
Claims32
A method comprising:
- detecting a command at a core of a processor having a plurality of cores, the command requesting a transition of the core to an idle state.
An apparatus comprising:
- a processor having a plurality of cores, the plurality of cores including a core to detect a command that requests a transition of the core to an idle state, the processor having hardware coordination logic to manage power consumption of the core based on the command and an idle state status of each of the plurality of cores.
A system comprising:
- a random access memory to store instructions;
- and
- a processor having a plurality of cores to execute the instructions, the plurality of cores including a core to detect a command that requests a transition of the core to an idle state, the processor having hardware coordination logic to manage power consumption of the core based on the command and an idle status of each of the plurality of cores.
A method comprising:
- detecting a command at a core of a processor having a plurality of cores, the command requesting a transition of the core to a C-state;
- initiating a dedicated power saving feature in the core before transitioning the core to the C-state;
- determining whether each of the plurality of the cores is active;
- if none of the plurality of cores is active, initiating a shared power saving feature, preventing external break events from reaching the plurality of cores and transitioning the plurality of cores to the C-state;
- if one or more of the plurality of cores is active, determining whether the C-state is associated with a resource that is shared by the plurality of cores;
- if the C-state is associated with a resource that is shared by the plurality of cores, transitioning the core to a tentative state until each of the plurality of cores has detected a command requesting a transition to the C-state;
- if the C-state is not associated with a resource that is shared by the plurality of cores, transitioning the core to the C-state;
- and
- halting execution of the core.
6 more elements
Dependencies are inferred from the claim text.