Apparatus and related method of coordinating north bridge and south bridge for controlling power saving state transition of a central processing unit

A method of controlling power-saving states of a chipset and a central processing unit, the chipset comprising a north bridge and a south bridge, each coupled to a connected indicator wire, the method comprising:

• transmitting a first or second indicating signal respectively to the connected indicator wire when the north bridge or the south bridge receives a bus master request;
• responding to whether the north bridge or the south bridge has transmitted the first or second indicating signal respectively by a state adjustment signal of the connected indicator wire;
• and
• performing a corresponding operation by the north bridge and south bridge according to the state adjustment signal of the connected indicator wire.

A computer system comprising:

• a central processing unit capable of operating in a high power-saving state and a low power-saving state;
• a north bridge comprising a first signal port capable of transmitting a first indicating signal;
• a south bridge comprising a second signal port capable of transmitting a second indicating signal;
• a connected indicator wire coupled between the first signal port and the second signal port, a signal of the connected indicator wire capable of responding to whether the north bridge or the south bridge has output the respective first or second indicating signal;
• the south bridge further comprising a control module;
• when the signal of the connected indicator wire detects the first or second indicating signal respectively transmitted by the north bridge or the south bridge, the control module is capable of controlling the central processing unit to operate at the low power-saving state.