Processor
OwnerKiyokazu Nishioka, Kazuhiko Tanaka +6inventors
InventorsKiyokazu Nishioka, Kazuhiko Tanaka, Yoshifumi Fujikawa, Toru Nojiri, Keiji Kojima, Koichi Terada, Yoshiki Kurokawa, Koji Hosoki
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Abstract
An object of the present invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
Claims1
A processor, comprising:
- a memory for storing an instruction code and data;
- an instruction code holding means for a plurality of instruction codes read from said memory;
- and
- a plurality of computing units operating in parallel according to the plurality of instruction codes held in said instruction code holding means;
- wherein each computing unit includes a plurality of computing devices and a plurality of access port register files, each of said plurality of computing devices reading a content of each of said register files from a corresponding access port for computation, and said plurality of computing units each having a same function.
Dependencies are inferred from the claim text.