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US 2006/0053258 A1Published application
Cache filtering using core indicators
OwnerYen-Cheng Liu, Krishnakanth Sistla +1inventors
InventorsYen-Cheng Liu, Krishnakanth Sistla, George Cai
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Abstract
A caching architecture within a microprocessor to filter core cache accesses. More particularly, embodiments of the invention relate to a technique to manage transactions, such as snoops, within a processor having a number of processor core caches and an inclusive shared cache.
Claims30
An apparatus comprising:
- an inclusive shared cache having an inclusive shared cache line and a core bit to indicate whether a processor core cache may have a copy of data stored within the inclusive shared cache line.
A system comprising:
- a processor having a plurality of cores, each of the plurality of cores having a dedicated core cache;
- an inclusive shared cache to store a copy of all of the data stored in the plurality of core caches, each line of the inclusive shared cache corresponding to a plurality of core bits to indicate which of the plurality of core caches may have a copy of data stored in the inclusive share cache line to which the plurality of core bits correspond.
A method comprising:
- initiating an access to a first cache;
- initiating an access to a second cache depending upon the state of a set of bits to indicate whether the second cache may contain a copy of data stored in the first cache;
- retrieving a copy of the data as a result of one of the accesses.
A multiple core processor comprising:
- a processor core;
- a processor core cache coupled to the processor core;
- a system bus interface;
- an inclusive shared cache having an inclusive shared cache line and a first means for indicating whether the processor core cache is guaranteed not to have the copy of data stored within the inclusive shared cache line.
1 more element
Dependencies are inferred from the claim text.