Side-by-side inverted memory address and command buses
AssigneeIntel Corporation
InventorsHoward David, Bill Nale
Life of this patent
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Abstract
Generating a pair of buses, each coupled to a common terminating device, each having a set of address signal lines that are coupled to a separate memory device, and driving one set of address signal lines with an address driven with true logic states while driving the other set of address signal lines with the same address, but driven to opposing logic states, to achieve a greater balance between the quantity of signals across both buses that are driven to a high state versus those that are driven to a low state.
Claims20
An apparatus comprising:
- a controlling device;
- a first bus coupled to the controlling device having a first set of address signal lines onto which an address is driven by the controlling device with the first set of address signal lines each driven to a true logic state;
- a second bus coupled to the controlling device having a second set of address signal lines onto which the address is driven by the controlling device with the second set of address signal lines each driven to an opposing logic state;
- a terminating device coupled to both the first and second sets of address signal lines;
- and
- a termination voltage power supply source coupled to the terminating device.
A computer system comprising:
- a controlling device;
- a first bus coupled to the controlling device having a first set of address signal lines onto which an address is driven by the controlling device with the first set of address signal lines each driven to a true logic state;
- a first memory device coupled to the first bus;
- a second bus coupled to the controlling device having a second set of address signal lines onto which the address is driven by the controlling device with the second set of address signal lines each driven to an opposing logic state;
- a second memory device coupled to the second bus;
- a third bus coupled to the controlling device having a third set of address signal lines through which the address is transmitted to the controlling device;
- a memory controller coupled to the third bus;
- and
- a processor coupled to the memory controller.
A method comprising:
- driving an address onto a first set of address signal lines of a first bus that is coupled to a first memory device and a terminating device such that the address signal lines of the first set of address signal lines are each driven to their true states;
- and
- driving the same address onto a second set of address signal lines of a second bus that is coupled to a second memory device and the terminating device such that the address signal lines of the second set of address signal lines are each drive to their opposing states.
A machine-accessible medium comprising code that when executed by a processor, causes the processor to:
- carry at least one test of a memory device coupled to a memory controller to determine which address signal lines of a bus coupled to the memory device are not used during at least one bus cycle in which at least a portion of an address is transmitted;
- and
- programming the memory controller to drive at least one of the address signal lines determined not to be used during the at least one bus cycle to a state that serves to achieve a greater balance between a quantity of address signal lines and command signal lines that are driven to a high state versus those that are driven to a low state.
Dependencies are inferred from the claim text.