Method and system for optimizing DMA channel selection
AssigneeQLOGIC, Corporation
InventorsBradley Sonksen, Kuangfu Chu, Rajendra Gandhi
Life of this patent
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AssigneeQLOGIC, Corporation
InventorsBradley Sonksen, Kuangfu Chu, Rajendra Gandhi
Estimating the term…
A host bus adapter coupled to a network and a host computing system is provided. The host bus adapter includes a direct memory access (“DMA”)mode detection module that receives a DMA channel identifier information from an arbitration module that receives requests from plural DMA channels, wherein the DMA mode detection module includes a DMA counter that counts a number of times a single DMA channel is exclusively serviced by the arbitration module and if the DMA counter value is equal to a threshold value, then the DMA mode detection module enables a single channel mode during which standard transaction rules are ignored for determining DMA request lengths for transferring data. The single channel mode is enabled for a certain duration. The host bus adapter includes a rule based segmentation logic that may be enabled and/or disabled by host bus adapter firmware and/or detection of a single channel mode condition.
A host bus adapter coupled to a network and a host computing system, comprising:
A system that allows a host computing system to communicate with plural devices over a network, comprising:
A host computing system that can communicate with plural devices over a network, comprising:
A method for transferring data between a host computing system and plural devices using a host bus adapter (“HBA”) coupled to a network, comprising:
Dependencies are inferred from the claim text.