Graphics processing logic with variable arithmetic logic unit control and method therefor
AssigneeATI Technologies, Inc.
InventorMichael Mantor
Life of this patent
Estimating the term…
Abstract
Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data representing which of the plurality of arithmetic logic units are not to receive data for processing. The graphics data processing logic also includes parallel ALU data packing logic that is operatively coupled to the plurality of arithmetic logic processing units and to the programmable storage element to pack data only for the plurality of arithmetic logic units identified by the data in the programmable storage element as being enabled.
Claims13
Graphics data processing logic comprising:
- a plurality of parallel arithmetic logic units that operate as a vector processor on at least one of pixel data and vertex data;
- a programmable storage element containing data representing which of the plurality of arithmetic logic units are not to receive data for processing;
- and
- parallel ALU data packing logic operatively coupled to the plurality of arithmetic logic units and to the programmable storage element and operative to pack data only for the plurality of arithmetic logic units identified by the data representing which of the plurality of arithmetic logic units that are not to receive data for processing.
Graphics data processing logic comprising:
- a plurality of sets of parallel arithmetic logic units that operate as a vector processor on at least one of pixel data and vertex data;
- a programmable storage element that includes a pixel processing control register and a vertex processing control register wherein the pixel processing control register stores pixel disable data indicating whether one or more of the plurality of sets of parallel ALUs are not to be used for pixel generation and wherein the vertex processing control register includes vertex disable data representing whether one or more of the sets of parallel ALUs are not to be used for vertex generation and further including clock control logic, operatively coupled to each of the plurality of parallel ALUs to disable a set of parallel ALUs if the both the pixel disable data and the vertex disable data indicate to disable a set of parallel ALUs;
- and
- parallel ALU data packing logic, operatively coupled to the plurality of arithmetic logic units and to the programmable storage element, that includes a vertex data packer and a pixel data packer each operative to pack respective data only for the set or sets of arithmetic logic units identified by the data representing which of the plurality of arithmetic logic units that are not to receive data for processing.
A method for processing graphics data comprising:
- storing data for a plurality of parallel arithmetic logic units that operate as a vector processor on at least one of pixel data and vertex data wherein the data represents which of the plurality of arithmetic logic units are not to receive data for processing;
- and
- packing data only for the plurality of arithmetic logic units identified by the data representing which of the plurality of arithmetic logic units that are not to receive data for processing.
A method for adjusting the processing and/or power level comprising:
- receiving input corresponding to a request for adjusting the processing and/or power level;
- and
- toggling an enable bit to activate or deactivate a subset of a plurality of parallel arithmetic logic units within a pipeline comprised of a plurality of ALUs.
A method for adjusting the processing and/or power level comprising:
- receiving an enable bit;
- and
- deactivating a subset of a plurality of parallel arithmetic logic units within a pipeline comprised of a plurality of ALUs responsive to said enable bit received.
Graphics data processing logic comprising:
- logic, operatively coupled to receive fuse bits associated with one or more defective arithmetic logic units of a plurality of parallel arithmetic logic units and operatively coupled to receive bits representing selectable disable bits operative to disable ALUs that remain based on the fuse bits.
Dependencies are inferred from the claim text.