Apparatus with redundant circuitry and method therefor

An apparatus with circuit redundancy comprising:

• a set of parallel arithmetic logic units (ALUs) divided into a plurality of subsets of parallel ALUs;
• a redundant parallel ALU;
• first data shifting logic, operatively coupled to a first subset of parallel ALUs and operative to shift input data to a neighboring ALU in the first subset;
• second data shifting logic, operatively coupled to a second subset of parallel ALUs in the set of parallel ALUs and operative to shift input data to a neighboring parallel ALU in the second subset;
• multiplexing logic operatively coupled to the redundant parallel ALU and to both the first and second data shifting logic to receive input data destined from an end ALU in each of the subsets of parallel ALUs;
• and
• third data shifting logic operatively coupled to output data from the parallel redundant ALU and to shift output data from affected parallel ALUs in a second and opposite direction to realign output of data for continued processing.

An apparatus with circuit redundancy comprising:

• a two dimensional array of arithmetic logic units (ALUs) logically arranged to have multiple sets of horizontal parallel ALUs that receive or output data in a common cycle;
• a redundant parallel ALU;
• first data shifting logic, operatively coupled to the two dimension array of ALUs and operative to shift input data for a defective ALU in the two dimensional array of ALUs in a first direction, to an ALU in a neighboring processing pipe and operative to shift input data for a last non defective ALU in a last processing pipe to the redundant parallel ALU;
• and
• second data shifting logic operatively coupled to output data from the parallel redundant ALU and to shift output data from affected parallel ALUs in a second and opposite direction to realign output of data for continued processing.

A graphics processing circuit comprising:

• a set of parallel vector scalar processing units (VP);
• a redundant parallel vector scalar processor;
• first data shifting logic, operatively coupled to the set of parallel VP's and operative to shift input data for a defective VP in a first direction, to a neighboring VP unit in the set and operative to shift input data for a last non defective VP in the set to the redundant parallel VP;
• and
• second data shifting logic operatively coupled to output data from the parallel redundant VP and to shift output data from affected parallel ALUs in a second and opposite direction to realign output of data for continued processing.