Strained silicon device manufacturing method

A microelectronic device comprising:

• a gate structure overlying a semiconductor substrate and for selectively operating a strained p-channel in the semiconductor substrate;
• source and drain regions, each comprising:
• a first doped region located adjacent to the channel and extending a first depth into the semiconductor substrate,
• a second doped region located adjacent to the first doped region and extending a second depth into the semiconductor substrate greater than the first depth, and
• a third doped region located adjacent to the second doped region and extending a third depth into the semiconductor substrate greater than the second depth.

A method of forming a p-channel transistor on a silicon substrate, comprising:

• forming a poly gate structure over the substrate;
• forming a lightly doped source/drain region in the substrate;
• forming an oxide liner adjacent to opposing side walls of the poly gate structure;
• etching a recess in the semiconductor substrate on opposing sides of the oxide liner;
• forming raised SiGe source/drain regions on either side of the oxide liner;
• forming a slim spacer over the oxide liner;
• implanting a source/drain dopant into the substrate including the SiGe regions;
• and
• providing a silicide region in the implanted SiGe regions.