Source driver with multi-channel shift register
AssigneeMagnaChip Semiconductor, Ltd.
InventorTae-Ho Jung
Life of this patent
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Abstract
A source driver for use in a display device having a shift register unit for sequentially activating output signals. The shift register unit includes a plurality of shift registers connected in series, wherein Nth shift register among the plurality of shift registers selects one of an output of a (N−1)th shift register and an output of a (N−A)th shift register according to a channel selection signal to thereby receive the selected signal, where A is a natural number which is greater than or equal to 2.
Claims19
A source driver for activating plural output signals comprising:
- a plurality of shift registers coupled in series, wherein, wherein Nth shift register among the plurality of shift registers selects one of an output of a (N−1)th shift register and an output of a (N−A)th shift register according to a channel selection signal to thereby receive the selected signal, where the A and the N are a natural number which is greater than or equal to 2.
A source driver having a shift register unit including a plurality of flip-flops each of which selects one of a first input data and a second input data in response to a first channel selection signal and a second channel selection signal and outputs the selected signal in synchronization with a clock signal, the source driver comprising:
- a first flip-flop for receiving a start signal as a fist and a second input data and for receiving a first control signal as a first and a second channel selection signals;
- a second flip-flop for receiving an output of the first flip-flop as a first and a second input data and for receiving a second control signal as a first and a second channel selection signals;
- a third flip-flop for receiving an output of the second flip-flop as a first and a second input data and for receiving a third control signal as a first and a second channel selection signals;
- a fourth flip-flop for receiving an output of the third flip-flop and the output of the second flip-flop as a first input data and a second input data respectively and for receiving a fourth control signal and the third control signal as a first channel selection signal and a second channel selection signal;
- a fifth flip-flop for receiving an output of the fourth flip-flop as a first and a second channel selection signals and for receiving an inverted second control signal as a first and a second channel selection signals;
- a sixth flip-flop for receiving an output of the fifth flip-flop and the output of the second flip-flop as a first input data and a second input data respectively and for receiving the second control signal and the inverted second control signal as a first channel selection signal and a second channel selection signal respectively;
- and
- a seventh flip-flop for receiving an output of the sixth flip-flop as a first and a second input data and for receiving the first control signal as a first and a second channel selection signals.
A source driver having a shift register unit including a plurality of flip-flops each of which selects one of a first input data and a second input data as a left input data and one of a third input data and a fourth input data as a right input data in response to a first channel selection signal and a second channel selection signal in order to select one of the left input data and the right input data according to a direction selection signal and output the selected signal in synchronization with a clock signal, the source driver comprising:
- a first flip-flop for receiving a start signal as a first and a second input data and for receiving an output of a second flip-flop and an output of a third flip-flop as a third input data and a fourth input data respectively and for receiving a first control signal as a first and a second channel selection signals;
- the second flip-flop for receiving an output of the first flip-flop as a first and a second input data and for receiving the output of the third flip-flop as a third and a fourth input data and for receiving a second control signal as first and a second channel selection signals;
- the third flip-flop for receiving the output of the second flip-flop and the output of the first flip-flop as a first input data and a second input data respectively and for receiving an output of a fourth flip-flop as a third and a fourth input data and for receiving the second control signal and an inverted second control signal as a first channel selection signal and a second channel selection signal respectively;
- and
- the fourth flip-flop for receiving the output of the third flip-flop as a first and a second input data and for receiving the start signal as a third and a fourth input data and for receiving the first control signal as a first and a second channel selection signals,
- wherein each of the first to the fourth flip-flops receives a same clock signal and a same direction selection signal.
The source driver as recited in claim 101 wherein the input data selection unit includes:
- a first AND gate for receiving the first input data and the first channel selection signal;
- a second AND gate for receiving the second input data and the second channel selection unit;
- a third AND gate for receiving the third input data and the first channel selection signal;
- a fourth AND gate for receiving the fourth input data and the second channel selection signal;
- a first NOR gate for receiving an output of the first AND gate and an output of the second AND gate to thereby generate the left input data;
- and
- a second NOR gate for receiving an output of the third AND gate and an output of the fourth AND gate to thereby generate the right input data.
A multi-channel shift register having a plurality of flip-flops connected in series, each of the flip-flops selects one of a first input data and a second input data in response to a first channel selection signal and a second channel selection signal and outputs the selected signal in synchronization with a clock signal, the multi-channel shift register comprising:
- a first flip-flop for receiving a start signal as a fist and a second input data and for receiving a first control signal as a first and a second channel selection signals;
- a second flip-flop for receiving an output of the first flip-flop as a first and a second input data and for receiving a second control signal as a first and a second channel selection signals;
- a third flip-flop for receiving an output of the second flip-flop as a first and a second input data and for receiving a third control signal as a first and a second channel selection signals;
- a fourth flip-flop for receiving an output of the third flip-flop and the output of the second flip-flop as a first input data and a second input data respectively and for receiving a fourth control signal and the third control signal as a first channel selection signal and a second channel selection signal;
- a fifth flip-flop for receiving an output of the fourth flip-flop as a first and a second channel selection signals and for receiving an inverted second control signal as a first and a second channel selection signals;
- a sixth flip-flop for receiving an output of the fifth flip-flop and the output of the second flip-flop as a first input data and a second input data respectively and for receiving the second control signal and the inverted second control signal as a first channel selection signal and a second channel selection signal respectively;
- and
- a seventh flip-flop for receiving an output of the sixth flip-flop as a first and a second input data and for receiving the first control signal as a first and a second channel selection signals.
A multi-channel shift register having a plurality of flip-flops each of which selects one of a first input data and a second input data as a left input data and one of a third input data and a fourth input data as a right input data in response to a first channel selection signal and a second channel selection signal in order to select one of the left input data and the right input data according to a direction selection signal and output the selected signal in synchronization with a clock signal, the multi-channel shift register comprising:
- a first flip-flop for receiving a start signal as a first and a second input data and for receiving an output of a second flip-flop and an output of a third flip-flop as a third input data and a fourth input data respectively and for receiving a first control signal as a first and a second channel selection signals;
- the second flip-flop for receiving an output of the first flip-flop as a first and a second input data and for receiving the output of the third flip-flop as a third and a fourth input data and for receiving a second control signal as first and a second channel selection signals;
- the third flip-flop for receiving the output of the second flip-flop and the output of the first flip-flop as a first input data and a second input data respectively and for receiving an output of a fourth flip-flop as a third and a fourth input data and for receiving the second control signal and an inverted second control signal as a first channel selection signal and a second channel selection signal respectively;
- and
- the fourth flip-flop for receiving the output of the third flip-flop as a first and a second input data and for receiving the start signal as a third and a fourth input data and for receiving the first control signal as a first and a second channel selection signals,
- wherein each of the first to the fourth flip-flops receives a same clock signal and a same direction selection signal.
Dependencies are inferred from the claim text.