Phase comparison circuit and cdr circuit
AssigneeNippon Telegraph and Telephone Corporation
InventorsYusuke Otomo, Masafumi Nogawa
Life of this patent
Estimating the term…
Abstract
Providing a CDR circuit having a stable clock extracting function and a data regenerating function with a high-speed data input process by reducing the operation speed of the phase comparator circuit. With a phase comparator circuit capable of operating with a clock signal whose period is 2 times the unit time width of the inputted data signal, the pulse width of the phase error signal, representing the difference in phase between the transition point of the data signal and the transition point of the clock signal, is extended as much as the unit time width of the data signal.
Claims8
A phase comparator circuit for operating with a clock signal whose period is 2 times the unit time width of an inputted data signal, said phase comparator circuit characterized in that;
- said data signal is inputted to a first latch circuit and a second latch circuit, said first latch circuit performs the latching operation thereof with a first clock signal, and said second latching circuit performs the latching operation thereof with the second clock signal, as being an inverted clock signal of said first clock signal;
- the output of said first latching circuit is inputted to a third latch circuit, the output of said second latch circuit is inputted to a fourth latch circuit, said third latch circuit performs the latching operation thereof with said second clock signal, and said fourth latch circuit performs the latching operation thereof with said first clock signal;
- and
- an exclusive OR of the output from said second latch circuit and the output from said third latch circuit is used as a first phase error signal, and an exclusive OR of the output from said first latch circuit and the output from said fourth latch circuit is used as second phase error signal.
A phase comparator circuit for operating with a clock signal whose period is 2 times the unit time width of an inputted data signal, said phase comparator circuit characterized in that;
- a first phase error signal, representing the phase difference between the transition point of said data signal and the rising edge of a first clock signal as the pulse width, is outputted;
- and
- a second phase error signal, representing the phase difference between the transition point of said data signal and the rising edge of a second clock signal as being the inverted clock signal of said first clock signal, is outputted.
A phase comparator circuit for operating with a clock signal whose period is 2 times the unit time width of an inputted data signal, said phase comparator circuit characterized in that;
- the pulse width of the phase error signal representing the phase difference between the transition point of said data signal and the transition point of said clock signal is extended by the time width corresponding to the unit time width of said data signal.
A CDR circuit including a phase comparator circuit, a charge pump circuit and a loop filter, operating with a clock signal whose period is 2 times the unit time width of an inputted data signal, and characterized in that;
- said phase comparator circuit outputs a first phase error signal, representing the pulse width as being the phase difference between the transition point of the said data signal and the rising edge of said clock signal, and a second phase error signal, representing the pulse width as being the phase difference between the transition point of said data signal and the falling edge of said clock signal;
- when the transition has occurred between two consecutive data in said data signal, said phase comparator circuit outputs a first reference signal, having a time width ranging from the falling edge of said clock signal to the rising edge of said clock signal, and a second reference signal, having a time width ranging from the rising edge of said clock signal to the falling edge of said clock signal;
- said charge pump circuit comprises a first charge pump circuit for receiving the input of said first phase error signal and the input of said reference signal, and a second charge pump circuit for receiving the input of said second phase error signal and said second reference signal;
- and
- the source current to flow into said loop filter according to the said first and second phase error signals and the sink current to flow into said loop filter according to said first and second reference signals are designed to become equal with each other when the phase of said data signal and the phase of said clock signal coincide with each other.
Dependencies are inferred from the claim text.