Synchronization device and semiconductor device

A synchronization device for receiving data on a plurality of channels and performing channel-to-channel synchronization and frame synchronization, comprising the following on each of the plurality of channels:

• a clock and data recovery circuit, which receives multiphase clock signals generated from a clock signal that is output from a clock source within the device, and a received data signal of the channel, for generating a data signal and a recovery clock signal;
• a first frequency divider circuit, which receives the recovery clock signal, for generating a frequency-divided clock signal from this clock signal;
• a phase detection control circuit for detecting a phase difference between the phase of the frequency-divided clock signal from said first frequency divider circuit and the phase of an internal clock signal supplied within the device and adjusted for skew, the clock signal being obtained by frequency dividing the clock signal from the clock source, and exercising control in such a manner that the phase of the frequency-divided clock signal and the phase of the internal clock signal will substantially coincide;
• a serial-to-parallel converter circuit, which receives the frequency-divided clock signal from said first frequency dividing circuit, for converting the data signal, which is output from said clock and data recovery circuit, to parallel data;
• a register array for holding the parallel data, which is output from said serial-to-parallel converter circuit, for a prescribed number of stages;
• and
• a frame detecting circuit for detecting a frame pattern from output signals of said serial-to-parallel converter circuit or from said serial-to-parallel converter circuit and said register array, and outputting a frame detection signal;
• said synchronization device further comprising the following shared by the plurality of channels:
• a detecting circuit, which receives the frame detection signal from said frame detecting circuit of each channel, for detecting, from among the plurality of channels, a channel on which a frame pattern was detected last;
• and
• a timing control circuit for exercising control in such a manner that timing of a frame head of the channel on which the frame pattern was detected last, the phase of the internal clock signal and the phase of the frequency-divided clock signal in the receiver circuits of the respective channels are shifted and adjusted so as to substantially coincide;
• wherein until the frame pattern is output in parallel from said serial-to-parallel converter circuit on the channel in which the frame pattern was detected last, parallel data signals that have been output from said serial-to-parallel converter circuits of the other channels are held in the register arrays of these other channels;
• and
• in the receiver circuits of the respective channels, frame-synchronized parallel data signals are output in unison using as a reference the detection timing of the frame pattern of the channel on which the frame pattern was detected last.