Method and system for a multi-channel signal synchronizer

A machine-readable storage having stored thereon, a computer program having at least one code section for processing signals the at least one code section being executable by a machine for causing the machine to perform steps comprising:

• receiving a plurality of clock signals from a plurality of clock signal sources, wherein at least a portion of said received plurality of clock signals are out of synchronization with at least a remaining portion of said received plurality of clock signals;
• receiving a plurality of data signals from a plurality of data signal sources, wherein at least a portion of said received plurality of data signals are out of synchronization with at least a remaining portion of said received plurality of data signals;
• synchronizing said received portion of said plurality of clock signals to said received remaining portion of said plurality of clock signals utilizing bit alignment;
• synchronizing said received portion of said plurality of data signals to said received remaining portion of said plurality of data signals utilizing said bit alignment and sample alignment;
• and
• generating a plurality of synchronized output signals based on said synchronized received plurality of clock signals and said synchronized received plurality of data signals.

A system for processing signals, the system comprising:

• circuitry for receiving a plurality of clock signals from a plurality of clock signal sources, wherein at least a portion of said received plurality of clock signals are out of synchronization with at least a remaining portion of said received plurality of clock signals;
• circuitry for receiving a plurality of data signals from a plurality of data signal sources, wherein at least a portion of said received plurality of data signals are out of synchronization with at least a remaining portion of said received plurality of data signals;
• circuitry for synchronizing said received portion of said plurality of clock signals to said received remaining portion of said plurality of clock signals utilizing bit alignment;
• circuitry for synchronizing said received portion of said plurality of data signals to said received remaining portion of said plurality of data signals utilizing said bit alignment and sample alignment;
• and
• circuitry for generating a plurality of synchronized output signals based on said synchronized received plurality of clock signals and said synchronized received plurality of data signals.