Back to results
US 2006/0050601 A1Published application
Semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorCheul Koo
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device processes external commands in parallel using divided clocks, which embodies a high-speed operation of a DRAM in increase of clock frequency. In the semiconductor memory device, command processing blocks are separated into row and column paths in parallel, and the command processing blocks connected in parallel are sequentially latched by clocks obtained by dividing input clocks applied externally, thereby improving the operation speed of the DRAM at high operation and reducing power consumption.
Claims18
A semiconductor memory device comprising:
- a clock generator for delaying an input clock for a predetermined time to generate a delay clock, and dividing the input clock to output a first division signal and a second division signal having an opposite phase to that of the first division signal;
- a latch unit for latching an input signal buffered synchronously with respect to the delay clock for a predetermined time;
- a first command processing means comprising a plurality of command processing blocks connected in parallel for latching and amplifying an output signal applied from the latch unit synchronously with respect to the first division signal and the second division signal;
- a second command processing means comprising a plurality of bank control blocks connected in parallel for generating a control signal to control row and column paths in response to an output signal applied from the first command processing means synchronously with respect to the first division signal and the second division signal;
- and
- a selection unit for selecting one of output signals from the second command processing means in response to the first division signal and the second division signal.
3 more elements
A semiconductor memory device comprising:
- a clock generator for delaying an input clock for a predetermined time to generate a delay clock, and dividing the input clock to output a first division signal and a second division signal having an opposite phase to that of the first division signal;
- a latch unit for latching a input signal buffered synchronously with respect to the delay clock for a predetermined time;
- a first command processing means for processing a predetermined operation command in response to an output signal applied from the latch unit synchronously with respect to the first division signal;
- a second command processing means for processing a predetermined operation command in response to an output signal applied from the latch unit synchronously with respect to the second division signal;
- and
- a selection unit for selecting one of output signals from the first command processing means and the second command processing means in response to the first division signal and the second division signal.
3 more elements
Dependencies are inferred from the claim text.