Circuit for verifying the write speed of SRAM cells
AssigneeLSI Logic Corporation
InventorsRamnath Venkatraman, Ruggero Castagnetti
Life of this patent
Estimating the term…
Abstract
A circuit for measuring the performance of a memory cell. The circuit includes a ring oscillator, which includes a plurality of memory cells. The performance of the memory cell can be determined from an oscillation frequency of the ring oscillator. The circuit accurately verifies the performance of the memory cell without modifying the memory cell. This avoids altering the transient AC characteristics of the memory cell when predicting its performance.
Claims52
A circuit for measuring the performance of a memory cell, the circuit comprising:
- a ring oscillator, wherein the ring oscillator comprises a plurality of memory cells, wherein the performance of the memory cell can be determined from an oscillation frequency of the ring oscillator.
A circuit for measuring the performance of a memory cell, the circuit comprising:
- a ring oscillator, wherein the ring oscillator comprises a plurality of memory cells, wherein the performance of the memory cell can be determined from an oscillation frequency of the ring oscillator, wherein the ring oscillator has a first cycle and a second cycle, wherein during the first cycle a data state zero is written to the plurality of memory cells, wherein during the second cycle a data state one is written to the plurality of memory cells, and wherein a ratio between the first cycle and the second cycle is used to determine transient characteristics of the memory cell.
A ring oscillator comprising:
- at least one inverter;
- and
- a NAND gate coupled to the at least one inverter;
- a plurality of repeating units coupled to the NAND gate, wherein the plurality of repeating units comprises:
- a memory cell of the plurality of memory cells, wherein the memory cell is adapted to be coupled to a wordline, to a first bitline, and to a second bitline;
- a first circuit coupled to the memory cell, wherein the first circuit comprises a first inverter coupled to the first bitline, and a transistor coupled to the first inverter and to the second bitline;
- and
- a second circuit coupled to the memory cell, wherein the second circuit comprises a second inverter coupled to the first inverter, and an OR gate coupled to the second inverter and to the wordline, wherein the performance of a memory cell can be determined from an oscillation frequency of the ring oscillator.
A system for measuring the performance of a memory cell, the system comprising:
- a plurality of memory cells;
- and
- a ring oscillator, wherein the plurality of memory cells are integrated into the ring oscillator, wherein the performance of the memory cell can be determined from an oscillation frequency of the ring oscillator.
A method for measuring the performance of a memory cell, the method comprising:
- providing a plurality of memory cells;
- providing a ring oscillator that incorporates the plurality of memory cells;
- and
- determining the performance of the memory cell from an oscillation frequency of the ring oscillator.
Dependencies are inferred from the claim text.