Semiconductor memory device with reduced leak current

Abstract

A semiconductor memory device includes a memory cell array, a decoder circuit configured to assert a decoding signal for selecting an access position in the memory cell array in response to an address signal supplied from an exterior, and a first circuit configured to put the decoding signal of the decoder circuit in an asserted state regardless of a value of the address signal in response to assertion of a standby signal supplied from the exterior.

Dependencies are inferred from the claim text.