# US 2006/0050591 A1 · Address coding method and address decoder for reducing sensing noise during refresh operation of memory device

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- Number: US 2006/0050591 A1
- Document ID: US20060050591A1
- Status: Published application
- Kind: A1
- Application number: 11/152,449
- Filed: 2005-06-14
- Published: 2006-03-09
- Earliest claimed: 2004-09-09
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Chul-Woo Park
- Web page: https://patentgrep.com/patent/US20060050591A1

## CPC

- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 2211/4065: Low level details of refresh operations
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An address coding method, which is performed by a memory device including a plurality of banks each being shared by at least two memory blocks, includes: activating adjacent banks shared by at least two memory blocks during a refresh operation of the memory device, and enabling the refresh operation in each bank alternately between the at least two memory blocks. The method includes activating adjacent banks shared by the at least two memory blocks during another operation of the memory device, and enabling the another operation in each bank alternately between the at least two memory blocks.

## Claims

### Claim 1

An address coding method, which is performed by a memory device including a plurality of banks each being shared by at least two memory blocks, comprising:
activating adjacent banks shared by the at least two memory blocks during a refresh operation of the memory device;
enabling the refresh operation in each bank alternately between the at least two memory blocks;
activating the adjacent banks shared by the at least two memory blocks during another operation of the memory device; and
enabling the another operation in each bank to one of the at least two memory blocks.

### Claim 2 (depends on 1)

The method of claim 1, wherein each of the at least two memory blocks has a unique data path.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
receiving an internal signal for enabling the refresh operation at a first plurality of multiplex units;
outputting the internal signal to a first plurality of bank decoders;
inverting the internal signal;
outputting an inverted internal signal to a second plurality of multiplex units;
outputting the inverted internal signal to a second plurality of bank decoders, each bank decoder corresponding to one of the adjacent banks;
receiving a row address signal at each bank decoder; and
activating a word line of each bank alternately between the at least two memory blocks, wherein a first bank of a first block receives the internal signal and a second bank of the first block adjacent to the first bank receives the inverted internal signal.

### Claim 4

A memory device including a plurality of banks each being shared by a plurality of upper memory blocks and a plurality of lower memory blocks, comprising:
coding address signals of adjacent banks for alternately activating the adjacent banks of the upper memory blocks and the lower memory blocks, during a refresh operation of the memory device; and
coding address signals of adjacent banks for activating the adjacent banks of one of the upper memory blocks and the lower memory blocks, during another operation of the memory device.

### Claim 5 (depends on 4)

The memory device of claim 4, further comprising a plurality of bank decoders, each bank decoder coupled to a corresponding bank, the plurality of bank decoders outputting the coding address signals, each coding address signal specifying a word line and a row address of each bank.

### Claim 6 (depends on 4)

The memory device of claim 4, wherein a bank shared between an upper memory block and a lower memory block is activated in one of the upper memory block and the lower memory block in response to the coding address signals and deactivated in the one of the upper memory block and the lower memory block in response to the coding address signals.

### Claim 7 (depends on 4)

The memory device of claim 4, wherein the coding address signal is output by a decoder in response to an internal signal output by a multiplex unit and a row address signal.

### Claim 8

An address decoder of a memory device having a structure in which a plurality of banks are shared by an upper memory block and a lower memory block, the address decoder comprising:
a plurality of multiplex units, each multiplex unit selecting one of an internal address signal and an external address signal, the plurality of multiplex units for allocating each of the plurality of banks to one of the upper memory block and the lower memory block, in response to a refresh signal; and
a plurality of bank decoders, each bank decoder connected to each of the plurality of banks, receiving the internal address signal or the external address signal output from the multiplex units with row address signals input to the memory device, decoding the received signals, and activating word lines in corresponding banks,
wherein during a refresh operation of the memory device, the multiplex units provide the internal address signal and an inverted signal of the internal address signal alternately to the bank decoders.

### Claim 9 (depends on 8)

The address decoder of claim 8, wherein the internal address signal is generated from the external address signal.

### Claim 10 (depends on 8)

The address decoder of claim 8, wherein each of the upper and lower memory blocks has a unique data path.

### Claim 11 (depends on 8)

The address decoder of claim 8, further comprising an inverter receiving the internal address signal and outputting the inverted signal of the internal address signal.

### Claim 12 (depends on 11)

The address decoder of claim 11, wherein the inverter is coupled to a subset of the plurality of multiplex units providing the inverted signal of the internal address signal.