Method and apparatus for operating nonvolatile memory cells in a series arrangement
AssigneeMacronix International Co., Ltd.
InventorChih Yeh
Life of this patent
Estimating the term…
Abstract
A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a series of memory cells, and an array of series of memory cells.
Claims46
A method of operating a nonvolatile memory array storing data as charge storage states, the nonvolatile memory including nonvolatile memory cells arranged in columns, each of the nonvolatile memory cells including a first and a second current carrying node in a substrate region, and including a charge storage structure, and one or more dielectric structures at least partly between the charge storage structure and a source of gate voltage and at least partly between the substrate region and the charge storage structure, the method comprising:
- performing one or more memory operations applying a bit line bias to a bit line, comprising:
- electrically connecting the bit line bias to a first end of a column of nonvolatile memory cells, the column arranged in a series such that adjacent first and second current carrying nodes of adjacent memory cells in the column are electrically connected;
- and
- electrically connecting the bit line bias to a second end of the column of nonvolatile memory cells.
A nonvolatile memory integrated circuit storing data as charge storage states, comprising:
- a nonvolatile memory array including a plurality of columns of memory cells, each memory cell including:
- a substrate region having a first current carrying node and a second current carrying node;
- a charge storage structure;
- one or more dielectric structures at least partly between the charge storage structure and the substrate region and at least partly between the charge storage structure and a source of gate voltage;
- wherein each column of the plurality of columns is arranged in a series having a first end and a second end such that adjacent first and second current carrying nodes of adjacent memory cells in said each column are electrically connected;
- a plurality of bit lines each having a corresponding column of the plurality of columns, wherein during at least one operation at least one bit line is electrically connected to the first end of the corresponding column and during at least one operation said at least one bit line is electrically connected to the second end of the corresponding column;
- and
- a plurality of word lines providing the gate voltage to the plurality of memory cells.
A nonvolatile memory integrated circuit storing data as charge storage states, comprising:
- a column of memory cells, each memory cell including:
- a substrate region having a first current carrying node and a second current carrying node;
- a charge storage structure;
- one or more dielectric structures at least partly between the charge storage structure and the substrate region and at least partly between the charge storage structure and a source of gate voltage;
- wherein the column is arranged in a series having a first end and a second end such that adjacent first and second current carrying nodes of adjacent memory cells in said each column are electrically connected;
- a bit line, wherein during at least one operation the bit line is electrically connected to the first end of the column and during at least one operation the bit line is electrically connected to the second end of the column;
- and
- a word line providing the gate voltage to the column of memory cells.
Dependencies are inferred from the claim text.