US 2006/0050550 A1Published application

High reliability triple redundant memory element with integrated testability and voting structures on each latch

AssigneeHewlett-Packard Development Company, L.P.

InventorsJohn Petersen, Hassan Naser, Jonathan Lotz

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Abstract

In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

A triple redundant latch for reducing soft errors comprising:

a) a first settable memory element;
b) a second settable memory element;
c) a third settable memory element;
d) a first voting structure;
e) a second voting structure;
f) a third voting structure;
g) a first buffer;
h) wherein an identical logic value is set in each settable memory element;
i) wherein inputs to the first voting structure are provided by the second settable memory element and the third settable memory element;
j) wherein inputs to the second voting structure are provided by the first settable memory element and the third settable memory element;
k) wherein inputs to the third voting structure are provided by the second settable memory element and the first settable memory element;
l) wherein an output of the first voting structure determines a logical value held on the first settable memory element after the first settable memory element, the second settable memory element, and the third settable memory element are set;
m) wherein an output of the second voting structure determines a logical value held on the second settable memory element after the first settable memory element, the second settable memory element, and the third settable memory element are set;
n) wherein an output of the third voting structure determines a logical value held on the third settable memory element after the first settable memory element, the second settable memory element, and the third settable memory element are set,
o) wherein scan data may be scanned into the second settable memory element;
p) wherein data may be scanned out of the second settable memory element into the buffer,
q) wherein data may be scanned from the buffer into third settable memory element;
r) wherein data may be scanned out of the third settable memory element;
s) wherein a propagation delay through the first settable memory element is the only propagation delay of the triple redundant latch.

16 more elements

Abstract

Claims20