US 2006/0049871 A1 · Multi-stage output buffer

Abstract

A multi-stage output buffer is disclosed having a differential input and a differential output. The output buffer includes an emitter follower circuit coupled to the differential input that is configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof. An emitter coupled pair circuit is coupled to the output of the emitter follower circuit, and is configured to amplify the signal and further isolate an input circuit when coupled to the differential input of the multi-stage output buffer from an external load when coupled to the differential output thereof. The buffer further includes a base-grounded transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer. The base-grounded transistor circuit is configured to reduce a load impedance at the output of the emitter coupled pair circuit, thereby improving a speed thereof. The base-grounded transistor circuit further improves decoupling of the external load from an input circuit when coupled thereto and increases the output power.

Claims26

Dependent claims

A multi-stage output buffer having a differential input and a differential output, comprising:

an emitter follower circuit coupled to the differential input, and configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof;
an emitter coupled pair circuit coupled to the output of the emitter follower circuit, wherein the emitter coupled pair circuit is configured to amplify the signal and further isolate an input circuit when coupled to the differential input of the multi-stage output buffer from an external load when coupled to the differential output thereof;
a differential base-grounded transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer, wherein the base-grounded transistor circuit is configured to reduce a load impedance at the output of the emitter coupled pair circuit, thereby improving a speed and signal amplitude of the buffer;
and
a bias current circuit coupled to the base-grounded transistor circuit, and configured to provide a DC bias current to keep transistors in the base-grounded transistor circuit from turning off when transistors in the emitter coupled pair circuit turn off, thereby further improving a speed, linearity and signal amplitude of the output buffer.

2 more elements

A multi-stage output buffer having a differential input and a differential output, comprising:

an impedance transformation means coupled to the inductive voltage dividing means, and operable to provide a large input impedance at an input thereof and a low output impedance at an output thereof to substantially decouple any succeeding stages from an input circuit at the differential input when coupled thereto;
a further decoupling and signal amplification means coupled to the impedance transformation means, and operable to further decouple the external load from the input circuit when coupled thereto, and to increase an output signal amplitude;
a load impedance reducing means coupled to the further decoupling and signal amplification means, and operable to reduce a load impedance at an output of the further decoupling and signal amplification means to improve a speed and signal amplitude of the output buffer means;
and
a bias current means coupled to the load impedance reducing means, and operable to provide a current to prevent active elements associated with the load impedance reducing means from turning off when active elements associated with the further decoupling and signal amplification means turn off, thereby improving a speed, linearity and output signal amplitude of the multi-stage output buffer.

2 more elements

Dependencies are inferred from the claim text.

Multi-stage output buffer

Life of this patent

Multi-stage output buffer

Life of this patent

Abstract

Claims26