Low-voltage CMOS switch with novel clock boosting scheme
AssigneeQUALCOMM Incorporated
InventorMustafa Keskin
Life of this patent
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Abstract
A method and apparatus for boosting the gate voltages of a CMOS switch used in an integrated circuit designed in a sub-micron CMOS process is disclosed. The CMOS switch is coupled to Vin and Vout nodes, and contains PMOS and NMOS gates. Two boosting circuits are used to change the voltage on the PMOS and NMOS gates, respectively. The voltage at the NMOS gate is boosted from VDD to (VDD+K×VDD). The voltage at the PMOS gate is decreased from VGND to (VGND−k×VGND). The factor k is chosen such that Vout can be sampled through the entire range of Vin=VGND to VDD, even where VDD approaches the sum of the absolute values of the threshold voltages of the respective PMOS and NMOS transistors.
Claims31
A circuit for boosting the supply voltages of a CMOS switch for use in an integrated circuit designed using a sub-micron process, the circuit using voltage sources of VDD and VGND, comprising:
- a CMOS switch comprising a PMOS transistor coupled to an NMOS transistor, the CMOS switch comprising a PMOS gate, an NMOS gate, an input Vin and an output Vout;
- a first boosting circuit coupled to the NMOS gate, the boosting circuit configured to use capacitor ratios and clocking signals to boost the voltage at the NMOS gate by the quantity (VDD+k×VDD);
- and
- a second boosting circuit coupled to the PMOS gate, the boosting circuit configured to use capacitor ratios and clocking signals to reduce the voltage at the PMOS gate by the quantity (VGND−k×VDD);
- wherein k comprises a factor chosen to allow sampling at Vout for values of Vin from VGND to VDD.
A circuit for boosting the supply voltages of a CMOS switch for use in an integrated circuit designed using a sub-micron process, the circuit using voltage source of VDD and VGND, comprising:
- a signal path comprising an input and an output;
- a CMOS switch coupled to the signal path between the input and the output;
- a boosting circuit coupled to a gate of the CMOS switch, the boosting circuit comprising a plurality of capacitors and transistors, the ratio of the plurality of capacitors configured to boost the voltage at the gate to a value sufficient to allow sampling of the output for values of the input between VGND and VDD.
A boosting circuit used in integrated circuits designed in sub-micron CMOS technology, the boosting circuit comprising an output, a node, three gate inputs, and the integrated circuit using a power source of VDD and VGND, comprising:
- a first PMOS transistor coupled to VDD, the output, and a first input of the three gate inputs;
- a first NMOS transistor coupled to VGND, the output, and a second of the three gate inputs;
- a first capacitor coupled to the output and to VGND;
- a second capacitor coupled to the output and to the node;
- a second PMOS transistor coupled to the node, VDD, and a second of the three gate inputs;
- and
- a second NMOS transistor coupled to the node, VGND, and the second of the three gate inputs.
A method for boosting gate voltages of a CMOS switch, the CMOS switch coupled to a signal path comprising Vin and Vout and including a PMOS gate and an NMOS gate, the CMOS switch using power sources of VDD and VGND and part of an integrated circuit designed in sub-micron CMOS technology, the method comprising:
- boosting a voltage value at the NMOS gate from VDD to a value of VDD+(k×VDD);
- and
- decreasing a voltage value at the PMOS gate from VGND to a value of VGND−(k×VGND);
- wherein
- k is chosen to enabling sampling at Vout over the range of Vin from VGND to VDD.
A boosting circuit for boosting the voltages at the gates of a CMOS switch, comprising:
- a signal path;
- CMOS switching means in the signal path for providing a Vin node and a Vout node, the CMOS switching means including NMOS and PMOS gates;
- NMOS boosting means for boosting a first voltage at the NMOS gate from VDD to a value of VDD+(VDD×k);
- PMOS boosting means for decreasing a second voltage at the PMOS gate from VGND to a value of VGND−(k×VDD);
- and
- sampling means at the Vout node for sampling the Vin signal over the range from VGND to VDD.
Dependencies are inferred from the claim text.