High performance adaptive load output buffer with fast switching of capacitive loads

An adaptive load output buffer comprising:

• a first set of series connected complementary cascode structures comprising respective p-channel and n-channel devices and having
• a first output node at a junction between the p-channel devices,
• a second output node at a junction between the complementary cascode structures, and
• a third output node at a junction between the n-channel devices;
• an output pad;
• first and second inverters;
• and
• at least one second set of series connected complementary cascode structures comprising a p-channel cascode structure and n-channel cascode structure and having
• a control terminal of the p-channel cascode structure connected to the first output node via said first inverter,
• a control terminal of the n-channel cascode structure connected to the third output node via the second inverter, and
• a common terminal between said p-channel and n-channel cascode structures connected to the second output node and said output pad.

An adaptive load output buffer comprising:

• a first set of series connected complementary cascode structures comprising respective p-channel and n-channel devices and having
• a first output node at a junction between the p-channel devices,
• a second output node at a junction between the complementary cascode structures, and
• a third output node at a junction between the n-channel devices;
• an output pad;
• a first inverter and a second inverter;
• and
• a plurality of second sets of series connected complementary cascode structures each comprising a p-channel cascode structure and n-channel cascode structure and having
• a control terminal of the p-channel cascode structure of an initial second set connected to the first output node via said first inverter with a control terminal of the p-channel cascode structure of a subsequent second set being provided a staggered input from the first inverter;
• a control terminal of the n-channel cascode structure of the initial second set connected to the third output node via the second inverter with a control terminal of the n-channel cascode structure of the subsequent second set being provided a staggered input from the second inverter;
• and
• each node between respective p-channel and n-channel cascode structures for the second sets connected together, to the second output node and to said output pad.

A method for operating an adaptive load output buffer comprising a first set of series connected complementary cascode structures comprising respective p-channel and n-channel devices and having a first output node at a junction between the p-channel devices, a second output node at a junction between the complementary cascode structures, and a third output node at a junction between the n-channel devices;

• and at least one second set of series connected complementary cascode structures comprising a p-channel cascode structure and n-channel cascode structure and having a control terminal of the p-channel cascode structure connected to the first output node via a first inverter, a control terminal of the n-channel cascode structure connected to the third output node via a second inverter, and a common terminal between said p-channel and n-channel cascode structures connected to the second output node and an output pad;
• the method comprising:
• charging/discharging the first/third node of the first set of series connected complementary cascode structures;
• and
• charging/discharging the output pad using the first/third node.