Decision feedback equalizer with bi-directional mode and lookup table

A circuit comprising:

• a first node having a first current sourced to the first node;
• a second node having a second current sourced to the second node;
• a voltage-to-current converter comprising a first input port having a first input voltage and a second input port having a second input voltage, the voltage-to-current converter to source a first output current to the first node and a second output current to the second node in response to the first and second input voltages;
• a latch having an evaluation mode, the latch connected to the first and second nodes to provide a sequence of logic signals for a sequence of evaluations, where each logic signal during an evaluation is indicative of whether the first current is greater in magnitude than the second current during the evaluation;
• a memory unit to store the logic signals;
• and
• a mapping circuit to source a first feedback current to the first node and a second feedback current to the second node as a function of a subset of the logic signals stored in the memory unit.

A circuit comprising:

• a first node;
• a second node;
• a voltage-to-current converter comprising a first input port, a second input port, a first output port connected to the first node, and a second output port connected to the second node;
• a latch connected to the first and second nodes to provide logic signals indicative of comparisons of a first current sourced into the first node and a second current sourced into the second node,
• a memory unit to store the logic signals provided by the latch during a sequence of comparisons;
• and
• a mapping circuit to source a first feedback current to the first node and a second feedback current to the second node as a function of a subset of the logic signals stored in the memory unit.

A circuit comprising:

• a first transmission line;
• a second transmission line;
• a first node;
• a second node;
• a voltage-to-current converter comprising a first input port connected to the first transmission line and a second input port connected to the second transmission line, the voltage-to-current comprising an output port connected to the first node and an output port connected to the second node;
• a latch having an evaluation mode, the latch connected to the first and second nodes to provide a sequence of logic signals for a sequence of evaluations, where each logic signal during an evaluation is indicative of whether a first current sourced to the first node is greater in magnitude than a second current sourced to the second node during the evaluation;
• a memory unit to store the logic signals;
• and
• a mapping circuit to source a first feedback current to the first node and a second feedback current to the second node as a function of a subset of the logic signals stored in the memory unit.