Package having dummy package substrate and method of fabricating the same
OwnerYoung-min Lee, Kun-dae Yeominventors
Life of this patent
Estimating the term…
Loading patent…
OwnerYoung-min Lee, Kun-dae Yeominventors
Estimating the term…
A package may include a stack of unit chip packages, and each unit chip package may include a printed circuit board. The printed circuit board may support a semiconductor chip and a connection terminal for connecting to an adjacent unit chip package within the stack. A dummy package substrate may be disposed on the semiconductor chip of the uppermost unit chip package for protecting the semiconductor chip of the uppermost unit chip package. A method of fabricating a package may involve stacking unit chip packages so that the printed circuit board of a lower unit chip package abuts against a solder bump of an upper unit chip package, and stacking a dummy package substrate on the printed circuit board of an uppermost unit chip package.
A package comprising:
A method comprising:
The method of claim 22, wherein the copper pattern is a meshed pattern.
Dependencies are inferred from the claim text.