US 2006/0049460 A1 · CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof

Abstract

In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

Claims43

Dependent claims

A semiconductor device comprising:

a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation, the second region have a second crystal orientation, wherein the second crystal orientation is different than the first crystal orientation;
a first logic gate formed on the first region;
and
a second logic gate formed on the second region, wherein the first region has a first preferred cleavage plane, the second region has a second preferred cleavage plane, and first preferred cleavage plane is not parallel to the second preferred cleavage plane.

1 more element

Dependencies are inferred from the claim text.

CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof

Life of this patent

CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof

Life of this patent

Abstract

Claims43