Method and apparatus for operating a string of charge trapping memory cells
AssigneeMacronix International Co., Ltd.
InventorChih Yeh
Life of this patent
Estimating the term…
Abstract
A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.
Claims54
A method of operating a plurality of memory cells arranged in series, the series having a first end coupled to a first pass transistor and a bit line and a second end coupled to a second pass transistor and the bit line, each memory cell comprising a gate, source and drain regions in a substrate region, and including a top dielectric, a charge trapping structure having parts corresponding to the source and drain regions, and a bottom dielectric between the gate and the substrate region, the method comprising:
- selecting a memory cell in the plurality of memory cells;
- turning on one of the first pass transistor and the second pass transistor to permit electrical coupling of the bit line to the source region or the drain region of the selected memory cell, thereby selecting part of the charge trapping structure corresponding to the source region or the drain region;
- and
- applying a first bias arrangement to determine a charge storage state of the selected part of the charge trapping structure.
A nonvolatile memory, comprising:
- a memory array including a plurality of columns, each column of the plurality of columns including a plurality of memory cells arranged in a series having a first end and a second end, each memory cell including:
- a substrate region including source and drain regions;
- a bottom dielectric coupled to the substrate region;
- a charge trapping structure coupled to the bottom dielectric having parts corresponding to the source and drain regions, each of the parts having a charge storage state;
- a top dielectric coupled to the charge trapping structure;
- and
- a gate coupled to the top dielectric;
- and
- a first pass transistor coupled to the first end of the series;
- a second pass transistor coupled to the second end of the series;
- a bit line coupled to the first pass transistor and the second pass transistor;
- and
- a plurality of word lines coupled to the gates of the plurality of memory cells;
- and
- logic coupled to the plurality of memory cells, said logic turning on one of the first pass transistor and the second pass transistor to permit electrical coupling of the bit line to the source region or the drain region of a memory cell of the plurality of memory cells, thereby selecting part of the charge trapping structure corresponding to the source region or the drain region.
A method of manufacturing a nonvolatile memory integrated circuit, comprising:
- providing a semiconductor substrate;
- providing a plurality of memory cells on the substrate arranged in a series having a first end and a second end, each memory cell including:
- a substrate region in the semiconductor substrate including source and drain regions;
- a bottom dielectric coupled to the substrate region;
- a charge trapping structure coupled to the bottom dielectric having parts corresponding to the source and drain regions, each of the parts having a charge storage state;
- a top dielectric coupled to the charge trapping structure;
- and
- a gate coupled to the top dielectric;
- and
- providing a first pass transistor coupled to the first end of the series;
- providing a second pass transistor coupled to the second end of the series;
- providing a bit line coupled to the first pass transistor and the second pass transistor;
- and
- providing a plurality of word lines coupled to the gates of the plurality of memory cells;
- and
- providing logic coupled to the plurality of memory cells, said logic turning on one of the first pass transistor and the second pass transistor to permit electrical coupling of the bit line to the source region or the drain region of a memory cell of the plurality of memory cells, thereby selecting part of the charge trapping structure corresponding to the source region or the drain region.
Dependencies are inferred from the claim text.