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US 2006/0049445 A1Published application
Dram having at least three layered impurity regions between channel holes and method of fabricating same
AssigneeSamsung Electronics Co., Ltd.
InventorsJin-Woo Lee, Yong-Sung Kim, Tae-Young Chung
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Abstract
Disclosed is a dynamic random access memory (DRAM) comprising a transistor having channel holes formed in the channel region thereof and cell gate structures formed in the channel holes. At least three layered impurity regions are formed in a semiconductor substrate between the channel holes and the at least three layered impurity regions form a source region for the transistor.
Claims23
A dynamic random access memory (DRAM), comprising:
- a device isolation layer formed in a semiconductor substrate, thereby defining an active region of the substrate;
- channel holes formed in the active region and surrounded by the device isolation layer;
- cell gate structures extending upward from the substrate and filling the channel holes;
- running gate structures formed on the device isolation layer in parallel with the cell gate structures;
- first impurity regions of first conductivity type formed in the substrate between the cell gate structures, and between the respective cell gate structures and the respective running gate structures;
- a second impurity region of first conductivity type formed in the substrate under the first impurity region formed between the cell gate structures;
- and,
- a third impurity region of second conductivity type formed in the substrate under the second impurity region.
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A method of fabricating a dynamic random access memory (DRAM), the method comprising:
- forming a device isolation layer in a semiconductor substrate, thereby defining an active region in the substrate;
- forming channel holes in the active region, the channel holes being surrounded by the device isolation layer;
- forming cell gate structures that extend upward from the substrate and in parallel with the running gate structures to fill the channel holes;
- forming running gate structures on the device isolation layer so as to be in parallel with the cell gate structures;
- implanting ions of first conductivity type in the substrate using the cell gate structures and running gate structures as a mask to form first impurity regions between the cell gate structures, and between the respective cell gate structures and the respective running gate structures;
- forming a second impurity region of first conductivity type under the first impurity region formed between the cell gate structures;
- and,
- forming a third impurity region of second conductivity type under the second impurity region.
5 more elements
Dependencies are inferred from the claim text.