Thin film transistor array panel

A thin film transistor array panel, comprising:

• a plurality of gate lines;
• a plurality of data lines intersecting the gate lines;
• a plurality of switching elements connected to the gate lines and the data lines;
• a plurality of pixel electrodes connected to the switching elements;
• an interlayer insulating layer formed between the gate lines and the data lines;
• a passivation layer covering the gate lines, the data lines, and the switching elements, the passivation layer having a plurality of first contact holes exposing portions of the data lines, wherein the switching elements and the pixel electrodes are connected through the first contact holes;
• a plurality of contact assistants formed on the passivation layer and connected to the data lines through a plurality of second contact holes in the passivation layer;
• and
• a plurality of assistant lines formed on the passivation layer, wherein the assistant lines overlap the data lines adjacent to the contact assistants.

A thin film transistor array panel, comprising:

• a plurality of data lines;
• a passivation layer covering the data lines;
• a plurality of contact assistants formed on the passivation layer and connected to the data lines through a plurality of contact holes in the passivation layer;
• and
• a plurality of assistant lines formed on the passivation layer, wherein the assistant lines overlap the data lines adjacent to the contact assistants.