Targeted optimization of buffer-tree logic
AssigneeInternational Business Machines Corporation
InventorsAnthony Drumm, Brian Wilson
Life of this patent
Estimating the term…
Abstract
Computationally efficient methods and systems for optimizing an integrated circuit (IC) design by targeting only a limited subsection of buffer trees in the buffer system for optimization are provided. By making intelligent decisions about which buffer trees to optimize, greater gains in design efficiency (e.g., as measured by reduced delays and/or wire length) may be realized at greatly reduced computational times when compared to conventional techniques that attempt to optimize each buffer tree.
Claims25
A method of optimizing buffer trees within an integrated circuit design, comprising:
- (a) identifying buffer trees existing in the design;
- (b) applying one or more selection criteria to the identified buffer trees;
- (c) building a list of buffer trees targeted for optimization comprising a limited subset of the identified buffer trees that satisfy the selection criteria;
- and
- (d) performing one or more buffer optimization algorithms on one or more of the targeted buffer trees in the list.
A method of optimizing a buffer tree of an integrated circuit design, comprising:
- (a) identifying buffer trees existing in the buffer tree;
- (b) building a list of buffer trees to target for optimization by, for each identified buffer tree,
- (i) determining if an area of a wire topology of the buffer tree without buffers exceeds a specified threshold area and the buffer tree with buffers exhibits negative slack timing, and
- (ii) if so, adding the buffer tree to the list;
- and
- (c) performing one or more buffer optimization algorithms on one or more of the targeted buffer trees in the list.
A computer-readable medium containing a program for optimizing a buffer sub-system of an integrated circuit design which, when executed by a processor, performs operations comprising:
- (a) identifying buffer trees existing in the buffer tree;
- (b) applying one or more selection criteria to the identified buffer trees;
- (c) building a list of buffer trees targeted for optimization comprising a limited subset of the identified buffer trees that satisfy the selection criteria;
- and
- (d) performing one or more buffer optimization algorithms on one or more of the targeted buffer trees in the list.
A computer system for optimizing a buffer tree of an integrated circuit design, comprising:
- a physical synthesis tool for placing logical components of the integrated circuit design;
- and
- a buffer tree optimizer included with or working in conjunction with the physical synthesis tool and configured to optimize the buffer tree by building a list containing a limited subset of buffer trees of the buffering system to target for optimization that that satisfy one or more selection criteria and performing one or more optimization algorithms on the selected buffer trees.
Dependencies are inferred from the claim text.