Cyclic code circuit with parallel output

Abstract

A cyclic code is generated by a circuit including a group of logic gates that generate one multiple-bit code segment from another multiple-bit code segment. The logic gates may, for example, receive B initial bits, where B is the degree of the generator polynomial, and generate one complete (2B−1)-bit code cycle, from which a clocked address generator and a barrel shifter select successive C-bit segments for output (C>1). Alternatively, the logic gates may receive a C-bit segment of the code from a register and generate the next C-bit segment, which is then stored in the register in synchronization with a clock signal. Either arrangement outputs C bits of code per clock pulse and therefore does not require a special high-frequency clock signal.

Dependencies are inferred from the claim text.