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US 2006/0041808 A1Published application
Test-pattern generation system, test-pattern analysis system, test-pattern generation method, test-pattern analysis method, and computer product
AssigneeFujitsu Limited
InventorKazuyuki Yamamura
Life of this patent
Estimating the term…
Abstract
An activation test sequence: 11XX0 with a test sequence ID: 8 is input to an ATPG to generate an activation test sequence: 11000. A propagation test sequence: 11XX1 with a test sequence ID: 8 is input to the ATPG to generate a propagation test sequence: 11011 with a test sequence ID: 9. A propagation test sequence: 11XX0 with a test sequence ID: 8 is input to the ATPG to generate a propagation test sequence: 11010 with a test sequence ID: 9. An activation test sequence: 11000 with a test sequence ID: 9, a propagation test sequence: 11011, and a propagation test sequence: 11010 are input to the ATPG to generate test patterns 11000XX, 11011XX, and 11011XH.
Claims12
A test-pattern generation system comprising:
- a net-list input unit that inputs a net list of a circuit;
- a first terminal-information generating unit that generates, for each terminal included in elements that form the circuit, first terminal information that includes identification information of one of the terminal and propagation route information that indicates identification information of another of the terminal that is located on a signal propagation route to one of the terminal based on the net list;
- a first fault-detection-information generating unit that generates first-fault detection information for detecting a fault in the terminal for each of the first terminal information generated;
- a test-sequence-information determining unit that determines whether the first fault-detection information includes identification information of a test sequence;
- a test-sequence generating unit that generates the test sequence for the first fault-detection information that is determined that the first fault-detection information includes the identification information of the test sequence by the test-sequence-information determining unit;
- and
- a test-pattern generating unit that generates a test pattern using the test sequence generated.
4 more elements
A test-pattern analysis system comprising:
- a net-list input unit that inputs a net list of a circuit;
- a first terminal-information generating unit that generates, for each terminal included in elements that form the circuit, first terminal information that includes identification information of one of the terminal and propagation route information that indicates identification information of another of the terminal that is located on a signal propagation route to one of the terminal based on the net list;
- a first fault-detection-information generating unit that generates first-fault detection information for detecting a fault in the terminal for each of the first terminal information generated;
- a test-sequence-information determining unit that determines whether the first fault-detection information includes identification information of a test sequence;
- a test-sequence generating unit that generates the test sequence for the first fault-detection information that is determined that the first fault-detection information includes the identification information of the test sequence by the test-sequence-information determining unit;
- a test-pattern generating unit that generates a test pattern using the test sequence generated;
- a simulation performing unit that performs a logic simulation on the circuit using the test pattern generated;
- an obtaining unit that obtains information that includes the test sequence with which the test pattern is generated, the first fault-detection information with which the test sequence is generated, and the fist terminal information of the terminal in which a fault is detected, when a result of the logic simulation includes an error;
- and
- an analyzing unit that analyzes the error included in the result using the information obtained.
7 more elements
A test-pattern generation method comprising:
- inputting a net list of a circuit;
- generating, for each terminal included in elements that form the circuit, first terminal information that includes identification information of one of the terminal and propagation route information that indicates identification information of another of the terminal that is located on a signal propagation route to the one of the terminal based on the net list;
- generating first-fault detection information for detecting a fault in the terminal for each of the first terminal information generated;
- determining whether the first fault-detection information includes identification information of a test sequence;
- generating the test sequence for the first fault-detection information that is determined that the first fault-detection information includes the identification information of the test sequence;
- and
- generating a test pattern using the test sequence generated.
4 more elements
A test-pattern analysis method comprising:
- inputting a net list of a circuit;
- generating, for each terminal included in elements that form the circuit, first terminal information that includes identification information of one of the terminal and propagation route information that indicates identification information of another of the terminal that is located on a signal propagation route to one of the terminal based on the net list;
- generating first-fault detection information for detecting a fault in the terminal for each of the first terminal information generated;
- determining whether the first fault-detection information includes identification information of a test sequence;
- generating the test sequence for the first fault-detection information that is determined that the first fault-detection information includes the identification information of the test sequence;
- generating a test pattern using the test sequence generated;
- performing a logic simulation on the circuit using the test pattern generated;
- obtaining information that includes the test sequence with which the test pattern is generated, the first fault-detection information with which the test sequence is generated, and the fist terminal information of the terminal in which a fault is detected, when a result of the logic simulation includes an error;
- and
- analyzing the error included in the result using the information obtained.
7 more elements
A computer-readable recording medium that stores a computer program for generating a test-pattern, the computer program making a computer execute:
- inputting a net list of a circuit;
- generating, for each terminal included in elements that form the circuit, first terminal information that includes identification information of one of the terminal and propagation route information that indicates identification information of another of the terminal that is located on a signal propagation route to the one of the terminal based on the net list;
- generating first-fault detection information for detecting a fault in the terminal for each of the first terminal information generated;
- determining whether the first fault-detection information includes identification information of a test sequence;
- generating the test sequence for the first fault-detection information that is determined that the first fault-detection information includes the identification information of the test sequence;
- and
- generating a test pattern using the test sequence generated.
4 more elements
A computer-readable recording medium that stores a computer program for analyzing a test-pattern, the computer program making a computer execute:
- inputting a net list of a circuit;
- generating, for each terminal included in elements that form the circuit, first terminal information that includes identification information of one of the terminal and propagation route information that indicates identification information of another of the terminal that is located on a signal propagation route to one of the terminal based on the net list;
- generating first-fault detection information for detecting a fault in the terminal for each of the first terminal information generated;
- determining whether the first fault-detection information includes identification information of a test sequence;
- generating the test sequence for the first fault-detection information that is determined that the first fault-detection information includes the identification information of the test sequence;
- generating a test pattern using the test sequence generated;
- performing a logic simulation on the circuit using the test pattern generated;
- obtaining information that includes the test sequence with which the test pattern is generated, the first fault-detection information with which the test sequence is generated, and the fist terminal information of the terminal in which a fault is detected, when a result of the logic simulation includes an error;
- and
- analyzing the error included in the result using the information obtained.
7 more elements
Dependencies are inferred from the claim text.