Integrated circuit
AssigneeNEC Electronics Corporation
InventorHiroaki Terai
Life of this patent
Estimating the term…
Abstract
An integrated circuit has a memory block including a RAM macro, a first scan circuit and a second scan circuit having a plurality of SFFs, and a serial access memory BIST circuit. The first scan circuit has an input scan FF group capable of supplying data to the memory block and the second scan circuit has an output scan FF group capable of receiving data from the memory block. In a first test mode, a normal scan test is performed. In a second test mode, the serial access memory BIST circuit outputs a BIST signal serially, and a selector selects and supplies the BIST signal to the input scan FF group, thereby testing the memory block.
Claims13
An integrated circuit comprising:
- a memory block including a memory macro;
- a scan circuit including a plurality of scan cells forming a scan path;
- and
- a Built-In Self Test (BIST) circuit generating a BIST signal, receiving a result signal indicating a test result of the memory block, and determining if the result signal-matches an expected value,
- wherein the plurality of scan cells include an input scan cell group capable of supplying data to the memory block and an output scan cell group capable of receiving data from the memory block,
- each scan cell of the input scan cell group receives a scan test signal from a scan cell of a previous stage in a first test mode and receives the BIST signal in a second test mode, and
- each scan cell of the output scan cell group receives a scan test signal from a scan cell of a previous stage in the first test mode and receives the result signal from the memory block in the second test mode.
Dependencies are inferred from the claim text.