Testing method for semiconductor device and testing circuit for semiconductor device
OwnerKohei Okada, Junji Moriinventors
Life of this patent
Estimating the term…
Abstract
There is provided a testing method for a semiconductor device which has a test object circuit, a non-test object circuit, and a plurality of register circuits which carry out fetching and holding of data based on a clock signal, the semiconductor device including a plurality of first scan chains configured such that the register circuits in the test object circuit are serially connected, and a plurality of second scan chains configured such that the register circuits in the non-test object circuit are serially connected, the testing method including: providing test data to the first and second scan chains, and inputting the clock signal to the first scan chains, not inputting the clock signal to the second scan chains.
Claims17
A testing method for a semiconductor device which has a test object circuit, a non-test object circuit, and a plurality of register circuits which carry out fetching and holding of data based on a clock signal, said semiconductor device including a plurality of first scan chains configured such that the register circuits in the test object circuit are serially connected, and a plurality of second scan chains configured such that the register circuits in the non-test object circuit are serially connected, said testing method comprising:
- providing test data to the first and second scan chains, and
- inputting the clock signal to the first scan chains, not inputting the clock signal to the second scan chains.
A testing method for a semiconductor device which has a test object circuit, a non-test object circuit, and a plurality of register circuits which carry out fetching and holding of data based on a clock signal, said semiconductor device including a plurality of first scan chains configured such that the register circuits in the test object circuit are serially connected, and a plurality of second scan chains configured such that the register circuits in the non-test object circuit are serially connected, said testing method comprising:
- providing test data to the first scan chains, and
- providing fixed data different from the test data to the second scan chains.
A testing circuit for a semiconductor device which has a test object circuit, a non-test object circuit and a plurality of register circuits, said testing circuit comprising:
- a plurality of first scan chains configured such that the register circuits in the test object circuit are serially connected;
- a plurality of second scan chains configured such that the register circuits in the non-test object circuit are serially connected;
- test data input terminals which provide test data to the first and second scan chains;
- test data output terminals which output test result data from the first scan chains;
- and
- a clock control circuit which, after the test data are input to the first and second scan chains, inputs a clock signal to the first scan chain, and does not input the clock signal to the second scan chain.
A testing circuit for a semiconductor device which has a test object circuit, a non-test object circuit and a plurality of register circuits, the testing circuit comprising:
- a plurality of first scan chains configured such that the register circuits in the test object circuit are serially connected;
- a plurality of second scan chains configured such that the register circuits in the non-test object circuit are serially connected;
- test data input terminals which provide test data to the first and second scan chains;
- test data output terminals which output test result data from the first and second scan chains;
- a first clock input terminal which provides a first clock signal to the first scan chains;
- and
- a second clock input terminal which provides a second clock signal to the second scan chains.
Dependencies are inferred from the claim text.