Apparatus and method for testing semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorChang-Ho Do
Life of this patent
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Abstract
A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode, and a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.
Claims46
A semiconductor memory device for performing a reliability test, comprising:
- a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode;
- a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode;
- and
- a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.
The semiconductor memory device as recited in claim 3, further comprising a local I/O line precharge block for precharging the local I/O line pair.
A semiconductor memory device for performing a reliability test, comprising:
- a test voltage generating block for generating a predetermined test voltage during a test mode;
- a local I/O line pair coupled to the test voltage generating block for receiving the predetermined test voltage in the test mode;
- and
- a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.
A semiconductor memory device for performing a reliability test, comprising:
- a local I/O line precharging block for generating a predetermined test voltage during a test mode and generating a core voltage as a local I/O line precharge voltage during a normal mode;
- a local I/O line pair coupled to the local I/O line precharging block for receiving the predetermined test voltage in the test mode;
- and
- a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.
A method for performing a background write test in the semiconductor memory device, comprising the steps of:
- a) generating at least one test command signal;
- b) preparing a test path for transmitting an predetermined test voltage outputted in response to the test command signal into a unit cell;
- c) supplying the predetermined test voltage to a local I/O line pair;
- and
- d) reading a stored data of the unit cell in order to conform a result of the background write test.
A semiconductor memory device for performing a background test, comprising:
- a test decision block for determining a goal and a range of the background write test and generating at least one test control signal;
- a test voltage generating block for outputting at least one predetermined test voltage to each data line in response to the test control signal outputted from the test decision block;
- and
- a test performing block coupled to the test voltage generating block through each data line for receiving the predetermined test voltage to check a fault of each data path and each unit cell.
Dependencies are inferred from the claim text.