Functional frequency testing of integrated circuits

A method of generating control signals, comprising:

• connecting an output of a first latch to an input of a second latch;
• connecting an output of said second latch to an input of a third latch;
• connecting said second latch through a feedback connection to an input of said first latch;
• connecting said third latch through feedback connections to said first and said second latches;
• coupling combinational logic to said first, second and third latches, said combinational logic having a test signal input, a test clock input and a functional clock input;
• coupling said feedback connection of said second latch through said combinational logic to a first control signal output;
• and
• coupling said first latch through said combinational logic to a second control signal output.

A control circuit, comprising:

• an output of a first latch connected to an input of a second latch, an output of said second latch connected to an input of a third latch, said second latch having a feedback connection to an input of said first latch and said third latch having feedback connections to said first and said second latches;
• said combinational logic coupled to said first, second and third latches, said combinational logic having a test signal input, a scan enable input and a functional clock input;
• and
• said feedback connection of said second latch further coupled through said combinational logic to a scan control output.

A method of generating a control signal, comprising:

• connecting an output of a first latch to an input of a second latch;
• connecting an output of said second latch to an input of a third latch;
• connecting said second latch through a feedback connection to an input of said first latch;
• connecting said third latch through feedback connections to said first and said second latches;
• coupling combinational logic to said first, second and third latches, said combinational logic having a test signal input, a scan enable input and a functional clock input;
• and
• coupling said feedback connection of said second latch through said combinational logic to a scan control output.

An integrated circuit, comprising:

• a test pin, a first test clock pin, a second test clock pin, a third test clock pin a functional clock pin, a scan-in pin, a scan-out pin and an enable pin;
• a test controller having a test input connected to said test pin, a first test clock input connected to said first test clock pin, a functional clock input connected to said functional clock pin, a first control output and a second control output;
• a clock splitter having a first clock input connected to said second test clock pin, a second clock input connected to said functional clock pin, a first control input connected to said first control output of said test controller, a second control input connected to said second control output and of said controller, an enable input connected to said enable pin, a ZB clock output and a ZC clock output;
• and
• an LSSD scan chain comprised of serially connected latches, a first stage of each latch having an first data input, a second data input and a C clock input connected to said ZC clock output of said clock splitter, an A CLK input connected to said third test clock pin, a second stage of each latch having a data output and a B clock input connected to said ZB clock output of said clock splitter, a data output of a previous latch connected to a first input pin of an immediately subsequent latch, a first data input of a first latch of said LSSD scan chain connected to said scan-in pin and a data output pin of a last scan chain latch of said scan chain connected to said scan-out pin.

A method of testing an integrated circuit, comprising:

• providing a test pin, a first test clock pin, a second test clock pin, a third clock pin, a functional clock pin, a scan-in pin, a scan-out pin and an enable pin;
• providing a test controller having a test input connected to said test pin, a first test clock input connected to said first test clock pin, a functional clock input connected to said functional clock pin, a first control output and a second control output;
• providing a clock splitter having a first clock input connected to said second test clock pin, a second clock input connected to said functional clock pin, a first control input connected to said first control output of said test controller, a second control input connected to said second control output and of said controller, an enable input connected to said enable pin, a ZB clock output and a ZC clock output;
• and
• providing an LSSD scan chain comprised of serially connected latches, a first stage of each latch having a first data input, a second data input and a C clock input connected to said ZC clock output of said clock splitter, an A clock input connected to said third test clock pin, a second stage of each latch having a data output and a B clock input connected to said ZB clock output of said clock splitter, a data output of a previous latch connected to a first input pin of an immediately subsequent latch, a first data input of a first latch of said LSSD scan chain connected to said scan-in pin and a data output pin of a last scan chain latch of said scan chain connected to said scan-out pin.