Test apparatus, phase adjusting method and memory controller
AssigneeAdvantest Corporation
InventorShinya Sato
Life of this patent
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Abstract
An inventive test apparatus has a timing comparator for obtaining an output value of an output signal outputted from a memory-under-test with timing of a strobe signal, a logical comparator for comparing the output value obtained by the timing comparator with an expected value and for outputting a comparison result and a phase adjustment control circuit for adjusting the timing of the strobe signal based on the comparison result outputted from the logical comparator. The inventive test apparatus further includes a first variable delay circuit for delaying and supplying the strobe signal to the timing comparator and the phase adjustment control circuit sets the delay effected by the first variable delay circuit based on the comparison result outputted from the logical comparator.
Claims14
A test apparatus for testing memory-under-tests, comprising:
- a timing comparator for obtaining an output value of an output signal outputted from said memory-under-test with timing of a strobe signal;
- a logical comparator for comparing said output value obtained by said timing comparator with an expected value generated in advance and for outputting the comparison result;
- and
- a phase adjustment control circuit for adjusting the timing of said strobe signal based on the comparison result outputted from said logical comparator.
A phase adjusting method for adjusting timing of an output signal outputted from a memory-under-test and a strobe signal, comprising:
- an output value obtaining step of obtaining an output value of said output signal outputted from said memory-under-test with timing of said strobe signal;
- a step of comparing said obtained output value with an expected value set in advance and outputting the comparison result;
- and
- a step of adjusting the timing of said strobe signal based on said comparison result.
A memory controller for controlling data writing and reading operations of a memory, comprising:
- a timing comparator for obtaining an output value of an output signal read out of said memory with timing of a strobe signal;
- a logical comparator for comparing said output value obtained by said timing comparator with an expected value set in advance and for outputting a comparison result;
- a phase adjustment control circuit for adjusting the timing of said strobe signal based on said comparison result outputted from said logical comparator;
- a temperature detecting section for detecting temperature of said memory or changes of temperature around said memory;
- and
- a re-calibration control section for adjusting again the timing of said strobe signal when the temperature change detected by said temperature detecting section exceeds a temperature change set in advance.
A memory controller for controlling data writing and reading operations of a memory, comprising:
- a timing comparator for obtaining an output value of an output signal read out of said memory with timing of a strobe signal;
- a logical comparator for comparing said output value obtained by said timing comparator with an expected value set in advance and for outputting a comparison result;
- a phase adjustment control circuit for adjusting the timing of said strobe signal based on said comparison result outputted from said logical comparator;
- and
- a re-calibration interval control section for measuring a time interval during which the timing of said strobe signal should be adjusted again based on said comparison result outputted from said logical comparator per elapsed time when data is written or read continuously to/from said memory.
Dependencies are inferred from the claim text.