Design techniques to increase testing efficiency

A semiconductor memory comprising:

• test mode logic for selecting between normal operation mode and test mode,
• a plurality of memory sub-blocks, wherein each memory sub-block further comprises:
• a plurality of memory cells forming a matrix, wherein each row of memory cells is coupled to one of a plurality of word lines and each column of memory cells is coupled to one of a plurality of bit lines,
• a memory address decoder connected to said plurality of word lines,
• a plurality of registers with sense and drive circuits, each of which is coupled to one of said plurality of bit lines,
• a plurality of Data in and Data out ports, and
• core address decode logic for selecting between said plurality of registers to write into and selecting between plurality of results from said bit lines to read from,
• wherein in at least one setting said test mode logic enables a plurality of memory sub-blocks to be written into at the same time.

A semiconductor device comprising:

• a plurality of functional blocks,
• a plurality of decoders, each with a plurality of outputs, and
• test mode logic for selecting between normal operation mode and test mode of said decoders,
• wherein in test mode said decoders enable a plurality of said decoders' outputs, and in normal mode said decoders enable one of said decoders' outputs.

A method for testing a semiconductor memory, said method comprising:

• setting said memory into test mode,
• said test mode enabling a plurality of addresses when writing, and enabling the comparison of internal read data with expected data and combining the results when reading,
• repeatedly writing and reading a plurality of addresses simultaneously, while collecting results,
• setting said memory into normal mode, said normal mode enabling a single address when writing and enabling providing the results from a single address when reading, and
• repeatedly writing and reading a plurality of addresses serially to test decode logic.

A method of testing a semiconductor device that includes a plurality of functional blocks, the method comprising:

• setting said device into test mode,
• repeatedly writing patterns and expected results to, and reading comparison results from, a plurality of said functional blocks simultaneously,
• setting said device into normal mode, said normal mode enabling single functional block reading, and
• repeatedly writing patterns to, and reading results from, said functional blocks, one functional block at a time.

A method of testing a semiconductor device that includes a plurality of functional blocks, the method comprising:

• setting said device into normal mode, said normal mode enabling single functional block reading,
• repeatedly writing patterns to, and reading results from, said functional blocks, one functional block at a time,
• setting said device into test mode, and
• repeatedly writing patterns and expected results to, and reading comparison results from, a plurality of said functional blocks simultaneously.