Jitter applying circuit and test apparatus

A test apparatus for testing jitter resistance of an electronic device, comprising:

• a pattern generator for generating a test pattern for testing said electronic device;
• a timing generator for generating a clock signal containing a phase jitter component corresponding to given jitter data;
• and
• a waveform forming device for inputting the test signal based on said test pattern to said electronic device with timing corresponding to said clock signal:
• said timing generator has a PLL circuit for generating an oscillating signal corresponding to a given reference signal;
• a variable delay circuit for outputting said clock signal in which said oscillating signal is delayed;
• a low-frequency application circuit for controlling oscillation frequency of said PLL circuit based on the low-frequency component of said jitter data to apply the low-frequency component of said phase jitter component to said oscillating signal;
• and
• a high-frequency application section for controlling a delay in said variable delay circuit based the high-frequency component of said jitter data to apply the high-frequency component of said phase jitter component to said clock signal.