Timing generator, test apparatus and skew adjusting method

A testing device testing an electronic device, comprising:

• a pattern generator operable to generate a test pattern for testing the electronic device;
• a timing generator operable to generate a timing signal of a desired period, said timing generator comprising:
• a set/reset latch that generates a rising edge of the timing signal according to a given set signal and generates a trailing edge of the timing signal according to a given reset signal;
• a set unit that supplies the set signal to the set/reset latch, said set unit comprising:
• a first variable delay circuit that delays a given reference clock to output a first set signal;
• a second variable delay circuit that delays the given reference clock to output a second set signal having a phase different from the first set signal;
• an OR circuit that computes a logical sum of the first set signal and the second set signal to generate the set signal;
• and
• a third variable delay circuit that delays the set signal output from the OR circuit to adjust a skew between the set signal and the reset signal, and
• a reset unit that supplies the reset signal to the set/reset latch,
• a waveform shaper operable to generate a test signal to be input to the electronic device based on the test pattern and the timing signal;
• and
• a judgment section operable to judge whether the good or bad quality of the electronic device based on an output signal output from the electronic device.

A skew adjusting method adjusting a skew between a first signal and a second signal in a timing generator that comprises:

• a first variable delay circuit that outputs the first signal;
• a second variable delay circuit that outputs the second signal;
• a first linearized memory that stores control data controlling the first variable delay circuit according to a given delay setting value in association with the each delay setting value;
• a second linearized memory that stores control data controlling the second variable delay circuit according to a given delay setting value in association with the each delay setting value;
• and
• an OR circuit that outputs a logical sum of the first signal and the second signal,
• the skew adjusting method comprising:
• a first period computing step of inputting the first signal to the first variable delay circuit via the OR circuit by feedback and computing a period by which the OR circuit outputs the first signal;
• a second period computing step of inputting the second signal to the second variable delay circuit via the OR circuit by feedback and computing a period by which the OR circuit outputs the second signal;
• a skew measuring step of computing a skew between the first signal and the second signal based on the difference between the period computed in said first period computing step and the period computed in said second period computing step;
• and
• a skew adjusting step of storing the control data to be stored in association with a setting value, which is obtained by adding a value according to the skew measured in said skew measuring step to the each delay setting value, on either the first linearized memory or the second linearized memory, in association with that delay setting value.