Engine for comparing a key with rules having defined ranges

A memory device, comprising:

• a memory including at least one rule;
• a memory controller including circuitry enabled to perform:
• (i) receiving a key;
• (ii) accessing a rule in the memory including a high and low values defining a range;
• (iii) concurrently comparing the key with the high and low values to determine whether the key falls within a range defined by the high and low values;
• (iv) indicating in status information the rule in response to the key falling within the defined range of the rule;
• and
• (v) performing an additional iteration of accessing a next rule, concurrently comparing the key with the high and low values of the next rule, and indicating in the status information the next rule in response to the key falling within a range defined by the next rule.

A network processor, comprising:

• a plurality of packet engines;
• a memory including at least one rule, wherein the memory is in communication with the packet engines;
• a memory controller including circuitry enabled to perform:
• (i) receiving a key from one of the packet engines;
• (ii) accessing a rule in the memory including a high and low values defining a range;
• (iii) concurrently comparing the key with the high and low values to determine whether the key falls within a range defined by the high and low values;
• (iv) indicating in status information the rule in response to the key falling within the defined range of the rule;
• and
• (v) performing an additional iteration of accessing a next rule, concurrently comparing the key with the high and low values of the next rule, and indicating in the status information the next rule in response to the key falling within a range defined by the next rule.

A network device, comprising:

• a switch fabric;
• and
• a plurality of line cards coupled to the switch fabric, wherein each line card includes a network processor, wherein at least one network processor on the line cards includes:
• (a) a plurality of packet engines;
• (b) a memory including at least one rule, wherein the memory is in communication with the packet engines;
• (c) a memory controller including circuitry enabled to perform:
• (i) receiving a key from one of the packet engines;
• (ii) accessing a rule in the memory including a high and low values defining a range;
• (iii) concurrently comparing the key with the high and low values to determine whether the key falls within a range defined by the high and low values;
• (iv) indicating in status information the rule in response to the key falling within the defined range of the rule;
• and
• (v) performing an additional iteration of accessing a next rule, concurrently comparing the key with the high and low values of the next rule, and indicating in the status information the next rule in response to the key falling 21 within a range defined by the next rule.

An article of manufacture enabled to cause operations to be performed, the operations comprising:

• receiving a key;
• accessing a rule including a high and low values defining a range;
• concurrently comparing the key with the high and low values to determine whether the key falls within a range defined by the high and low values;
• indicating in status information the rule in response to the key falling within the defined range of the rule;
• and
• performing an additional iteration of accessing a next rule, concurrently comparing the key with the high and low values of the next rule, and indicating in the status information the next rule in response to the key falling within a range defined by the next rule.