Latency-aware replacement system and method for cache memories
AssigneeInternational Business Machines Corporation
InventorsZhigang Hu, William Reohr
Life of this patent
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Abstract
A method for replacing cache lines in a computer system having a non-uniform set associative cache memory is disclosed. The method incorporates access latency as an additional factor into the existing ranking guidelines for replacement of a line, the higher the rank of the line the sooner that it is likely to be evicted from the cache. Among a group of highest ranking cache lines in a cache set, the cache line chosen to be replaced is one that provides the lowest latency access to a requesting entity, such as a processor. The distance separating the requesting entity from the memory partition where the cache line is stored most affects access latency.
Claims20
A method for caching memory to account for non-uniform access latencies, comprising steps of:
- determining a latency difference among lines mapped to a memory device;
- in accordance with a replacement policy, ranking the lines in the arranged memory device;
- and
- selecting for replacement, a line with a smallest latency from among lines with a lowest priority grouping.
A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for caching memory to account for non-uniform access latencies, the method steps comprising:
- determining a latency difference among lines mapped to a memory device;
- in accordance with a replacement policy, ranking the lines in the arranged memory device;
- and
- selecting for replacement, a line with a smallest latency from among lines with a lowest priority grouping.
A method for caching memory to account for non-uniform access latencies, comprising steps of:
- determining a latency difference among lines mapped to a memory device by associating selection circuits with portions of the arranged memory device such that each selection circuit determines the latency for lines and manages line selection for a requesting entity;
- in accordance with a replacement policy, ranking the lines in the memory device;
- and
- selecting for replacement, a line with a smallest latency from among lines with a lowest priority grouping in accordance with a selection circuit associated with the requesting entity.
A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for caching memory to account for non-uniform access latencies, the method steps comprising:
- determining a latency difference among lines mapped to a memory device by associating selection circuits with portions of the arranged memory device such that each selection circuit determines the latency for lines and manages line selection for a requesting entity;
- in accordance with a replacement policy, ranking the lines in the memory device;
- and
- selecting for replacement, a line with a smallest latency from among lines with a lowest priority grouping in accordance with a selection circuit associated with the requesting entity.
A cache system comprising:
- a cache servicing at least one requesting entity;
- a replacement policy which determines priority rankings for cache lines to be replaced during memory operations;
- and
- a selection circuit which determines latency differences among the cache lines and selects, for replacement, a cache line that has a lowest latency to the at least one requesting entity from among the cache lines with a lowest priority grouping.
Dependencies are inferred from the claim text.