Dual port memory with asymmetric inputs and outputs, device, system and method
AssigneeMicron Technology, Inc.
InventorJoo Choi
Life of this patent
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Abstract
An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device with the write bus width being different from the read bus width. A memory system including the asymmetric memory interface, memory controller and memory device is disclosed. The asymmetric nature of inputs and outputs reduces pin count by avoiding symmetric replication of bus widths for inputs and outputs. A method of accessing data in a memory device is also disclosed.
Claims31
An asymmetric memory interface, comprising:
- an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller;
- and
- an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device, the write bus width being different from the read bus width.
A memory system, comprising:
- a memory controller;
- a memory device;
- and
- an asymmetric interface coupling the memory controller with the memory device, the asymmetric interface including:
- an asymmetric read data interface of a read bus width configured to transfer data from the memory device to the memory controller;
- and
- an asymmetric write data interface of a write bus width configured to transfer data from the memory controller to the memory device, the write bus width being different from the read bus width.
A memory device, comprising:
- a memory array;
- and
- an interface configured to operably couple with an asymmetric interface for coupling a memory controller with the memory device, the interface including:
- an asymmetric read data interface of a read bus width configured to transfer data from the memory device to the memory controller;
- and
- an asymmetric write data interface of a write bus width configured to transfer data from the memory controller to the memory device, the write bus width being different from the read bus width.
An electronic system, comprising:
- a processor device;
- a memory controller coupled to the processor device;
- and
- an asymmetric memory interface, comprising:
- an asymmetric read data interface of a read bus width configured to transfer data from a memory device to the memory controller;
- and
- an asymmetric write data interface of a write bus width configured to transfer data from the memory controller to the memory device, the write bus width being different from the read bus width.
A method of accessing data in a memory device, comprising:
- writing data from a memory controller over an asymmetric write data interface of a write bus width to a memory device;
- storing the data in the memory device;
- and
- reading the data from the memory device over an asymmetric read data interface of a read bus width to the memory controller, the write bus width being different from the read bus width.
Dependencies are inferred from the claim text.