Back to results
US 2006/0040482 A1Published application
Mos transistor and fabrication thereof
AssigneeUnited Microelectronics Corp.
InventorsChih-Wei Yang, Yi-Sheng Hsieh, Wei-Min Lin, Wen-Tai Chiang, Wei-Tsun Shiau
Life of this patent
Estimating the term…
Abstract
A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.
Claims13
A method for fabricating a MOS transistor, comprising:
- forming a gate dielectric layer on a substrate;
- forming a first barrier layer on the gate dielectric layer;
- forming an interlayer on the first barrier layer;
- forming a work-function-dominating layer on the interlayer;
- forming a second barrier layer on the work-function-dominating layer;
- forming a poly-Si layer on the second barrier layer;
- patterning the poly-Si layer, the second barrier layer, the work-function-dominating layer, the interlayer and the first barrier layer into a gate;
- and
- forming a source/drain in the substrate beside the gate.
6 more elements
Dependencies are inferred from the claim text.