Source/drain structure for high performance sub 0.1 micron transistors
AssigneeSharp Laboratories of America, Inc.
InventorSheng Hsu
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Abstract
An asymmetric transistor structure comprising a gate structure with a drain halo ion implantation region, without any halo ion implantation region source region is provided. Methods of forming a transistor structure are also provided. An angled halo ion implant is preformed at an angle using ions of the same type as the well to form a drain halo ion implantation region, while protecting the source region to avoid forming a source halo region.
Claims22
A method of forming a transistor structure comprising:
- providing a substrate with an isolated well;
- forming a gate stack overlying the substrate;
- performing a source/drain extension ion implant;
- forming sidewalls;
- performing a drain halo ion implant without performing a source halo ion implant;
- and
- performing a source/drain ion implant.
A transistor structure comprising a gate structure overlying a channel region interposed between a source region and a drain region within a doped well;
- wherein the drain region comprises a drain halo ion implantation region, and the source region does not include a halo ion implantation region.
Dependencies are inferred from the claim text.